Quoting Akash Asthana (2019-12-16 01:25:51)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml[...]
new file mode 100644
index 0000000..2c3b911
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -0,0 +1,196 @@
+Shouldn't there be a minItems: 1 here? And then you should specify the order?
+ "serial@[0-9]+$":
+ type: object
+ description: GENI Serial Engine based UART Controller.
+
+ properties:
+ compatible:
+ enum:
+ - qcom,geni-uart
+ - qcom,geni-debug-uart
+
+ reg:
+ description: GENI Serial Engine register address and length.
+
+ interrupts:
+ description: Contains UART core and wakeup interrupts for wakeup
+ capable UART devices. We configure wakeup interrupt
+ on UART RX line using TLMM interrupt controller.
+ maxItems: 2
Presumably something like
interrupts:
minItems: 1
maxItems: 2
items:
- description: UART core irq
- description: Wakeup irq (RX GPIO)