Re: [PATCH 3/4] phy: qcom-qmp: Add optional SW reset

[Manu Gautam]

On 12/20/2019 6:19 AM, cang@xxxxxxxxxxxxxx wrote:
> On 2019-12-20 08:22, cang@xxxxxxxxxxxxxx wrote:
>> On 2019-12-19 23:04, Vinod Koul wrote:
>>> For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
>>> then deassert it, so add optional has_sw_reset flag and use that to
>>> configure the QPHY_SW_RESET register.
>>>
>>> Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx>
>>> ---
>>> Âdrivers/phy/qualcomm/phy-qcom-qmp.c | 10 ++++++++++
>>> Â1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
>>> b/drivers/phy/qualcomm/phy-qcom-qmp.c
>>> index 06f971ca518e..80304b7cd895 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
>>> @@ -1023,6 +1023,9 @@ struct qmp_phy_cfg {
>>>
>>> ÂÂÂÂ /* true, if PCS block has no separate SW_RESET register */
>>> ÂÂÂÂ bool no_pcs_sw_reset;
>>> +
>>> +ÂÂÂ /* true if sw reset needs to be invoked */
>>> +ÂÂÂ bool has_sw_reset;
>>> Â};
>>>
>>> Â/**
>>> @@ -1391,6 +1394,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
>>>
>>> ÂÂÂÂ .is_dual_lane_phyÂÂÂ = true,
>>> ÂÂÂÂ .no_pcs_sw_resetÂÂÂ = true,
>>> +ÂÂÂ .has_sw_resetÂÂÂÂÂÂÂ = true,
>>> Â};
>>>
>>> Âstatic void qcom_qmp_phy_configure(void __iomem *base,
>>> @@ -1475,6 +1479,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
>>> ÂÂÂÂ }
>>>
>>> +ÂÂÂ if (cfg->has_sw_reset)
>>> +ÂÂÂÂÂÂÂ qphy_setbits(serdes, cfg->regs[QPHY_SW_RESET], SW_RESET);
>>> +
>>
>> Are you sure you want to set this in the serdes register? QPHY_SW_RESET
>> is in its pcs register.
>>
>>> ÂÂÂÂ if (cfg->has_phy_com_ctrl)
>>> ÂÂÂÂÂÂÂÂ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SW_PWRDN);
>>> @@ -1651,6 +1658,9 @@ static int qcom_qmp_phy_enable(struct phy *phy)
>>> ÂÂÂÂ if (cfg->has_phy_dp_com_ctrl)
>>> ÂÂÂÂÂÂÂÂ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
>>>
>>> +ÂÂÂ if (cfg->has_sw_reset)
>>> +ÂÂÂÂÂÂÂ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
>>> +
>>
>> Yet you are clearing it from pcs register.
>>
>> Regards,
>> Can Guo
>>
>>> ÂÂÂÂ /* start SerDes and Phy-Coding-Sublayer */
>>> ÂÂÂÂ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
>
> I thought your change would be like this
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 8e642a6..a4ab4b7 100755
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -166,6 +166,7 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = {
> Â};
>
> Âstatic const unsigned int sm8150_ufsphy_regs_layout[] = {
> +ÂÂÂÂÂÂ [QPHY_SW_RESET]ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ = 0x08,
> ÂÂÂÂÂÂÂ [QPHY_START_CTRL]ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ = 0x00,
> ÂÂÂÂÂÂÂ [QPHY_PCS_READY_STATUS]ÂÂÂÂÂÂÂÂ = 0x180,
> Â};
> @@ -1390,7 +1391,6 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> ÂÂÂÂÂÂÂ .pwrdn_ctrlÂÂÂÂÂÂÂÂÂÂÂÂ = SW_PWRDN,
>
> ÂÂÂÂÂÂÂ .is_dual_lane_phyÂÂÂÂÂÂ = true,
> -ÂÂÂÂÂÂ .no_pcs_sw_resetÂÂÂÂÂÂÂ = true,


This makes sense to me.

> Â};
>
> Âstatic void qcom_qmp_phy_configure(void __iomem *base,
> @@ -1475,6 +1475,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
> ÂÂÂÂÂÂÂ }
>
> +ÂÂÂÂÂÂ if ((cfg->type == PHY_TYPE_UFS) && (!cfg->no_pcs_sw_reset))
> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂ qphy_setbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
> +


This change is not needed as POR value of SW_RESET bit is '1' which will be
set as part of GCC or clk_reset.
We just need to clear this bit which code already takes care of.


> ÂÂÂÂÂÂÂ if (cfg->has_phy_com_ctrl)
> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SW_PWRDN);
>
> Regards,
> Can Guo.

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project