Re: [PATCH 1/4] PCI: dwc: Add new feature to skip core initialization

From: Vidya Sagar
Date: Fri Jan 03 2020 - 04:40:50 EST

On 12/5/2019 3:34 PM, Kishon Vijay Abraham I wrote:


On 13/11/19 2:38 pm, Vidya Sagar wrote:
Add a new feature 'skip_core_init' that can be set by platform drivers
of devices that do not have their core registers available until reference
clock from host is available (Ex:- Tegra194) to indicate DesignWare
endpoint mode sub-system to not perform core registers initialization.
Existing dw_pcie_ep_init() is refactored and all the code that touches
registers is extracted to form a new API dw_pcie_ep_init_complete() that
can be called later by platform drivers setting 'skip_core_init' to '1'.

No. pci_epc_features should only use constant values. This is used by function drivers to know the controller capabilities.
Yes. I'm going to set EPC features as constant values in pcie-tegra194.c driver.
I'm going to rewrite this commit message in the next patch.

Thanks
Kishon


Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
---
 .../pci/controller/dwc/pcie-designware-ep.c | 72 +++++++++++--------
 drivers/pci/controller/dwc/pcie-designware.h | 6 ++
 include/linux/pci-epc.h | 1 +
 3 files changed, 51 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 3dd2e2697294..06f4379be8a3 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -492,19 +492,53 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
ÂÂÂÂÂ return 0;
 }
-int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
 {
+ÂÂÂ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ÂÂÂ unsigned int offset;
+ÂÂÂ unsigned int nbars;
+ÂÂÂ u8 hdr_type;
+ÂÂÂ u32 reg;
ÂÂÂÂÂ int i;
+
+ÂÂÂ hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
+ÂÂÂ if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
+ÂÂÂÂÂÂÂ dev_err(pci->dev,
+ÂÂÂÂÂÂÂÂÂÂÂ "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
+ÂÂÂÂÂÂÂÂÂÂÂ hdr_type);
+ÂÂÂÂÂÂÂ return -EIO;
+ÂÂÂ }
+
+ÂÂÂ ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
+
+ÂÂÂ ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
+
+ÂÂÂ offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
+ÂÂÂ if (offset) {
+ÂÂÂÂÂÂÂ reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
+ÂÂÂÂÂÂÂ nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
+ÂÂÂÂÂÂÂÂÂÂÂ PCI_REBAR_CTRL_NBAR_SHIFT;
+
+ÂÂÂÂÂÂÂ dw_pcie_dbi_ro_wr_en(pci);
+ÂÂÂÂÂÂÂ for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
+ÂÂÂÂÂÂÂÂÂÂÂ dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
+ÂÂÂÂÂÂÂ dw_pcie_dbi_ro_wr_dis(pci);
+ÂÂÂ }
+
+ÂÂÂ dw_pcie_setup(pci);
+
+ÂÂÂ return 0;
+}
+
+int dw_pcie_ep_init(struct dw_pcie_ep *ep)
+{
ÂÂÂÂÂ int ret;
-ÂÂÂ u32 reg;
ÂÂÂÂÂ void *addr;
-ÂÂÂ u8 hdr_type;
-ÂÂÂ unsigned int nbars;
-ÂÂÂ unsigned int offset;
ÂÂÂÂÂ struct pci_epc *epc;
ÂÂÂÂÂ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
ÂÂÂÂÂ struct device *dev = pci->dev;
ÂÂÂÂÂ struct device_node *np = dev->of_node;
+ÂÂÂ const struct pci_epc_features *epc_features;
ÂÂÂÂÂ if (!pci->dbi_base || !pci->dbi_base2) {
ÂÂÂÂÂÂÂÂÂ dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
@@ -563,13 +597,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ÂÂÂÂÂ if (ep->ops->ep_init)
ÂÂÂÂÂÂÂÂÂ ep->ops->ep_init(ep);
-ÂÂÂ hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
-ÂÂÂ if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
-ÂÂÂÂÂÂÂ dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
-ÂÂÂÂÂÂÂÂÂÂÂ hdr_type);
-ÂÂÂÂÂÂÂ return -EIO;
-ÂÂÂ }
-
ÂÂÂÂÂ ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
ÂÂÂÂÂ if (ret < 0)
ÂÂÂÂÂÂÂÂÂ epc->max_functions = 1;
@@ -587,23 +614,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ÂÂÂÂÂÂÂÂÂ dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
ÂÂÂÂÂÂÂÂÂ return -ENOMEM;
ÂÂÂÂÂ }
-ÂÂÂ ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
-ÂÂÂ ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
-
-ÂÂÂ offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
-ÂÂÂ if (offset) {
-ÂÂÂÂÂÂÂ reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
-ÂÂÂÂÂÂÂ nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
-ÂÂÂÂÂÂÂÂÂÂÂ PCI_REBAR_CTRL_NBAR_SHIFT;
-
-ÂÂÂÂÂÂÂ dw_pcie_dbi_ro_wr_en(pci);
-ÂÂÂÂÂÂÂ for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
-ÂÂÂÂÂÂÂÂÂÂÂ dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
-ÂÂÂÂÂÂÂ dw_pcie_dbi_ro_wr_dis(pci);
+ÂÂÂ if (ep->ops->get_features) {
+ÂÂÂÂÂÂÂ epc_features = ep->ops->get_features(ep);
+ÂÂÂÂÂÂÂ if (epc_features->skip_core_init)
+ÂÂÂÂÂÂÂÂÂÂÂ return 0;
ÂÂÂÂÂ }
-ÂÂÂ dw_pcie_setup(pci);
-
-ÂÂÂ return 0;
+ÂÂÂ return dw_pcie_ep_init_complete(ep);
 }
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 5accdd6bc388..340783e9032e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -399,6 +399,7 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
 #ifdef CONFIG_PCIE_DW_EP
 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
+int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -416,6 +417,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ÂÂÂÂÂ return 0;
 }
+static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
+{
+ÂÂÂ return 0;
+}
+
 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
 }
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 36644ccd32ac..241e6a6f39fb 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -121,6 +121,7 @@ struct pci_epc_features {
ÂÂÂÂÂ u8ÂÂÂ bar_fixed_64bit;
ÂÂÂÂÂ u64ÂÂÂ bar_fixed_size[PCI_STD_NUM_BARS];
ÂÂÂÂÂ size_tÂÂÂ align;
+ÂÂÂ boolÂÂÂ skip_core_init;
 };
 #define to_pci_epc(device) container_of((device), struct pci_epc, dev)