+
+ÂÂÂ if (sts & SWRM_INTERRUPT_STATUS_CMD_ERROR) {
+ÂÂÂÂÂÂÂ ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
+ÂÂÂÂÂÂÂ dev_err_ratelimited(ctrl->dev,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "CMD error, fifo status 0x%x\n",
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ value);
+ÂÂÂÂÂÂÂ ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
+ÂÂÂ }
+
+ÂÂÂ if ((sts & SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED) ||
+ÂÂÂÂÂÂÂ sts & SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS)
+ÂÂÂÂÂÂÂ schedule_work(&ctrl->slave_work);
+
+ÂÂÂ ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
is it intentional to clear the interrupts first, before doing additional checks?
No, I can move it to right to the end!
Or could it be done immediately after reading the status. It's not clear to me if the position of this clear matters, and if yes you should probably add a comment?
Am not 100% if it matters, but Ideally I would like clear the interrupt source before clearing the interrupt.
+The rest looks fine. nice work.
+ÂÂÂ if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED) {
+ÂÂÂÂÂÂÂ spin_lock_irqsave(&ctrl->comp_lock, flags);
+ÂÂÂÂÂÂÂ if (ctrl->comp)
+ÂÂÂÂÂÂÂÂÂÂÂ complete(ctrl->comp);
+ÂÂÂÂÂÂÂ spin_unlock_irqrestore(&ctrl->comp_lock, flags);
+ÂÂÂ }
+
+ÂÂÂ return IRQ_HANDLED;