[PATCH v3 2/3] drm/armada: optionally enable the peripheral clock

[Lubomir Rintel]

It needs to be enabled (at least on MMP2) in order for the register
writes to LCDC to work.

Signed-off-by: Lubomir Rintel <lkundrak@xxxxx>
---
 drivers/gpu/drm/armada/armada_crtc.c | 7 +++++++
 drivers/gpu/drm/armada/armada_crtc.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index da9ba8be8b097..0f343bf584c8c 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -772,6 +772,7 @@ static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
 
 	of_node_put(dcrtc->crtc.port);
 
+	clk_disable_unprepare(dcrtc->periphclk);
 	kfree(dcrtc);
 }
 
@@ -928,6 +929,11 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
 	dcrtc->clk = ERR_PTR(-EINVAL);
 	dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
 
+	dcrtc->periphclk = devm_clk_get(dev, "periph");
+	if (IS_ERR(dcrtc->periphclk))
+		dcrtc->periphclk = NULL;
+	WARN_ON(clk_prepare_enable(dcrtc->periphclk));
+
 	endpoint = of_get_next_child(port, NULL);
 	of_property_read_u32(endpoint, "bus-width", &bus_width);
 	of_node_put(endpoint);
@@ -1015,6 +1021,7 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
 err_crtc_init:
 	primary->funcs->destroy(primary);
 err_crtc:
+	clk_disable_unprepare(dcrtc->periphclk);
 	kfree(dcrtc);
 
 	return ret;
diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h
index b21267d1745f1..48fc974a65808 100644
--- a/drivers/gpu/drm/armada/armada_crtc.h
+++ b/drivers/gpu/drm/armada/armada_crtc.h
@@ -39,6 +39,7 @@ struct armada_crtc {
 	void			*variant_data;
 	unsigned		num;
 	void __iomem		*base;
+	struct clk		*periphclk;
 	struct clk		*clk;
 	struct {
 		uint32_t	spu_v_h_total;
-- 
2.24.1