Re: [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset

[Paul Walmsley]

On Sun, 5 Jan 2020, guoren@xxxxxxxxxx wrote:

> From: Guo Ren <ren_guo@xxxxxxxxx>
> 
> CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
> ISA Register misa. Every bit:1 indicate a feature, so we should beqz
> reset_done when there is no F/D bit in csr_msia register.
> 
> Signed-off-by: Guo Ren <ren_guo@xxxxxxxxx>

Thanks Guo Ren, queued for v5.5-rc.


- Paul