Re: [PATCH] x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR
From: Josh Poimboeuf
Date: Wed Jan 15 2020 - 16:15:26 EST
On Fri, Jan 10, 2020 at 02:50:54PM -0800, Pawan Gupta wrote:
> /proc/cpuinfo currently reports Hardware Lock Elision (HLE) feature to
> be present on boot cpu even if it was disabled during the bootup. This
> is because cpuinfo_x86->x86_capability HLE bit is not updated after TSX
> state is changed via a new MSR IA32_TSX_CTRL.
>
> Update the cached HLE bit also since it is expected to change after an
> update to CPUID_CLEAR bit in MSR IA32_TSX_CTRL.
>
> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@xxxxxxxxxxxxxxx>
> Tested-by: Neelima Krishnan <neelima.krishnan@xxxxxxxxx>
> Reviewed-by: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>
>From the Intel TAA deep dive page [1], it says:
"On processors that enumerate IA32_ARCH_CAPABILITIES[TSX_CTRL] (bit
7)=1, HLE prefix hints are always ignored."
So if the CPU has IA32_TSX_CTRL, HLE is implicitly disabled, so why
would the HLE bit have been set in CPUID in the first place?
[1] https://software.intel.com/security-software-guidance/insights/deep-dive-intel-transactional-synchronization-extensions-intel-tsx-asynchronous-abort
--
Josh