Re: [v3] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC

[Andy Shevchenko]

On Wed, Jan 29, 2020 at 04:13:39PM +0100, Thomas Gleixner wrote:
> Hans de Goede <hdegoede@xxxxxxxxxx> writes:
> > On 29-01-2020 15:14, Andy Shevchenko wrote:
> >>> The only one which is possibly suspicious here is this line:
> >>>
> >>>   * 0111:   25 * 32 /  9  =  88.8889 MHz
> >>>
> >>> The SDM says 88.9 MHz for this one.
> 
> I trust math more than the SDM :)
> 
> >> Anyway it seems need to be fixed as well.
> >> 
> >> Btw, why we are mentioning 20 / 6 and 28 / 6 when arithmetically
> >> it's the same as 10 / 3 and 14 / 3?
> >
> > I copied the BYT values from Thomas' email and I guess he did not
> > get around to simplifying them, I'll use the simplified versions
> > for my patch.
> 
> Too tired, too lazy :)
> 
> Andy, can you please make sure that people inside Intel who can look
> into the secrit documentation confirm what we are aiming for?
> 
> Ideally they should provide the X-tal frequency and the mult/div pair
> themself :)

So, I don't have access to the CPU core documentation (and may be will not be
given), nevertheless I dug a bit to what I have for Cherrytrail. So, the XTAL
is 19.2MHz, which becomes 100MHz and 1600MHz by some root PLL, then, the latter
two frequencies are being used by another PLL to provide a reference clock (*)
to PLL which derives CPU clock.

*) According to colleagues of mine it's a fixed rate source.

That's all what I have.

-- 
With Best Regards,
Andy Shevchenko