+ some people possibly interested in this for the Altera platforms (see below)Thank you for adding the team and respective members, let's see.
Hi all,
This is about moving the cadence qspi driver (which is used on TI, Altera FPGAs
and a new Intel SoC) to spi-mem.Vadivel asked me to include some Altera people
in the loop (see below), as this is the only platform currently untested,
I think.
Right now, I'm not in the position to test this myself as we're currently stuck
on an older RT kernel, so I cannot test with HEAD.
Feel free to involve other Intel/Altera if you're interested in that peripheral
not being broke for socfpga in one of the next releases :-)
On Wed, Jan 29, 2020 at 10:18 AM Ramuthevar, Vadivel MuruganX
<vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote:
Hi,OK, done that. I mainly know them from U-Boot development, so I'm not sure
Thank you for the query and confirmation.
On 29/1/2020 4:31 PM, Simon Goldschmidt wrote:
On Wed, Jan 29, 2020 at 8:25 AM Ramuthevar,Vadivel MuruganX
<vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote:
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx>
Add support for the Cadence QSPI controller. This controller is
present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs.
This driver has been tested on the Intel LGM SoCs.
So it has been tested on LGM and Vignesh gave his ok for TI. Is there anyone
in the loop by now checking that this is valid for the 3rd platform using this
(Altera)?
Or am I wrong in thinking that this driver is meant to replace
drivers/mtd/spi-nor/cadence-quadspi.c used on that platform?
Absolutely , You are right, this driver is meant to replace to drivers/mtd/spi-nor/cadence-quadspi.c
for Intel, TI and Altera SoC's using Cadence-QSPI IP.
Meanwhile we have adapted to spi-mem framework (to support spi-nor/nand)and also didn't change the existing
functionalities of spi-nor flash operations like hw_init/read/write/erase in drivers/mtd/spi-nor/cadence-quadspi.c,
so it works fine (might be in Altera as well).
Already I checked that Graham Moore <grmoore@xxxxxxxxxxxxxxxxxxxxx> who has submitted the existing driver patches to upstream,
His mail-id is bouncing back, then I decided that you are the right person to ask, could you please add them in loop if you know the team
(socfpga platform engineers).
who's responsible for the Linux drivers...
Regards,
Simon
Regards
Vadivel
Regards,
Simon