Re: [v12 2/2] clk: ls1028a: Add clock driver for Display output interface
From: Stephen Boyd
Date: Thu Jan 30 2020 - 19:32:11 EST
Quoting Wen He (2019-12-13 00:34:02)
> Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
> as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
> integer division and range of the display output pixel clock's 27-594MHz.
>
> Signed-off-by: Wen He <wen.he_1@xxxxxxx>
> Signed-off-by: Michael Walle <michael@xxxxxxxx>
> ---
Applied to clk-next