On Mon, Feb 3, 2020 at 10:33 PM Eddie James <eajames@xxxxxxxxxxxxxxxxxx> wrote:
On 1/30/20 10:37 AM, Andy Shevchenko wrote:...
On Wed, Jan 29, 2020 at 10:09 PM Eddie James <eajames@xxxxxxxxxxxxx> wrote:
Why to have duplication then?+ struct device *dev;Isn't fsl->dev the same?
Perhaps kernel doc to explain the difference?
No, it's not the same, as dev here is the SPI controller. I'll add a
comment.
...+ struct fsi_device *fsi;
Why not to call put_unaligned() how the tail in this case (it's 0 or+ for (i = 0; i < num_bytes; ++i)Redundant & 0xffULL part.
+ rx[i] = (u8)((in >> (8 * ((num_bytes - 1) - i))) & 0xffULL);
Isn't it NIH of get_unalinged_be64 / le64 or something similar?
No, these are shift in/out operations. The read register will also have
previous operations data in them and must be extracted with only the
correct number of bytes.
can be easily made to be 0) will affect the result?
Ditto.+ return num_bytes;Ditto as for above function. (put_unaligned ...)
+}
+static int fsi_spi_data_out(u64 *out, const u8 *tx, int len)
+{
...+}
It's way too long function to read. Indentation level also can improve+static int fsi_spi_transfer_data(struct fsi_spi *ctx,Can you refactor to tx and rx parts?
+ struct spi_transfer *transfer)
+{
Why?
readability.
That's basically what refactoring is for.
...+ return 0;
+}
One statement, but *two* lines.+ if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |Missed {} ?
+ SPI_FSI_CLOCK_CFG_ECC_DISABLE |
+ SPI_FSI_CLOCK_CFG_MODE |
+ SPI_FSI_CLOCK_CFG_SCK_RECV_DEL |
+ SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg)
+ rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
+ wanted_clock_cfg);
No? It's one line under the if.
What does checkpatch.pl tell you about this?