[PATCH v4 11/13] phy: cadence-torrent: Use regmap to read and write DPTX PHY registers

From: Yuti Amonkar
Date: Thu Feb 06 2020 - 01:11:40 EST

Next message: Yuti Amonkar: "[PATCH v4 10/13] phy: cadence-torrent: Use regmap to read and write Torrent PHY registers"
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From: Swapnil Jakhade <sjakhade@xxxxxxxxxxx>

Use regmap to read and write DPTX specific PHY registers.

Signed-off-by: Swapnil Jakhade <sjakhade@xxxxxxxxxxx>
Signed-off-by: Yuti Amonkar <yamonkar@xxxxxxxxxxx>
---
drivers/phy/cadence/phy-cadence-torrent.c | 169 +++++++++++++---------
1 file changed, 100 insertions(+), 69 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 027667a17ebe..0e03d3cb4c23 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -45,11 +45,12 @@
#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
(0xE000 << (block_offset))

+#define TORRENT_DPTX_PHY_OFFSET 0x0
+
/*
* register offsets from DPTX PHY register block base (i.e MHDP
* register base + 0x30a00)
*/
-#define PHY_AUX_CONFIG 0x00
#define PHY_AUX_CTRL 0x04
#define PHY_RESET 0x20
#define PMA_TX_ELEC_IDLE_MASK 0xF0U
@@ -65,8 +66,6 @@
#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
#define PHY_PMA_CMN_READY 0x34
-#define PHY_PMA_XCVR_TX_VMARGIN 0x38
-#define PHY_PMA_XCVR_TX_DEEMPH 0x3c

/*
* register offsets from SD0801 PHY register block base (i.e MHDP
@@ -179,6 +178,9 @@ static const struct reg_field phy_pma_cmn_ctrl_2 =
static const struct reg_field phy_pma_pll_raw_ctrl =
REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);

+static const struct reg_field phy_reset_ctrl =
+ REG_FIELD(PHY_RESET, 8, 8);
+
static const struct of_device_id cdns_torrent_phy_of_match[];

struct cdns_torrent_phy {
@@ -195,9 +197,11 @@ struct cdns_torrent_phy {
struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
+ struct regmap *regmap_dptx_phy_reg;
struct regmap_field *phy_pll_cfg;
struct regmap_field *phy_pma_cmn_ctrl_2;
struct regmap_field *phy_pma_pll_raw_ctrl;
+ struct regmap_field *phy_reset_ctrl;
};

enum phy_powerstate {
@@ -228,12 +232,6 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
unsigned int lane);
static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
u32 rate, u32 num_lanes);
-static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
- unsigned int offset,
- unsigned char start_bit,
- unsigned char num_bits,
- unsigned int val);
-
static int cdns_torrent_dp_configure(struct phy *phy,
union phy_configure_opts *opts);
static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
@@ -277,6 +275,27 @@ static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
return 0;
}

+static int cdns_regmap_dptx_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct cdns_regmap_cdb_context *ctx = context;
+ u32 offset = reg;
+
+ writel(val, ctx->base + offset);
+
+ return 0;
+}
+
+static int cdns_regmap_dptx_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct cdns_regmap_cdb_context *ctx = context;
+ u32 offset = reg;
+
+ *val = readl(ctx->base + offset);
+ return 0;
+}
+
#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
{ \
.name = "torrent_tx_lane" n "_cdb", \
@@ -333,6 +352,14 @@ static struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
.reg_read = cdns_regmap_read,
};

+static struct regmap_config cdns_torrent_dptx_phy_config = {
+ .name = "torrent_dptx_phy",
+ .reg_stride = 1,
+ .fast_io = true,
+ .reg_write = cdns_regmap_dptx_write,
+ .reg_read = cdns_regmap_dptx_read,
+};
+
/* PHY mmr access functions */

static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
@@ -350,21 +377,18 @@ static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)

/* DPTX mmr access functions */

-static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy,
- u32 offset, u32 val)
+static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
{
- writel(val, cdns_phy->base + offset);
+ regmap_write(regmap, offset, val);
}

-static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
+static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
{
- return readl(cdns_phy->base + offset);
-}
+ u32 val;

-#define cdns_torrent_dp_read_poll_timeout(cdns_phy, offset, val, cond, \
- delay_us, timeout_us) \
- readl_poll_timeout((cdns_phy)->base + (offset), \
- val, cond, delay_us, timeout_us)
+ regmap_read(regmap, offset, &val);
+ return val;
+}

/*
* Structure used to store values of PHY registers for voltage-related
@@ -439,6 +463,8 @@ static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
{
u32 rd_val;
u32 ret;
+ struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
+
/*
* Used to determine, which bits to check for or enable in
* PHY_PMA_XCVR_PLLCLK_EN register.
@@ -470,14 +496,14 @@ static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
else
pll_val = 0x00000000;

- cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
+ cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);

/* Wait for acknowledgment from PHY. */
- ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
- PHY_PMA_XCVR_PLLCLK_EN_ACK,
- rd_val,
- (rd_val & pll_bits) == pll_val,
- 0, POLL_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(regmap,
+ PHY_PMA_XCVR_PLLCLK_EN_ACK,
+ rd_val,
+ (rd_val & pll_bits) == pll_val,
+ 0, POLL_TIMEOUT_US);
ndelay(100);
return ret;
}
@@ -601,9 +627,10 @@ static int cdns_torrent_dp_verify_config(struct cdns_torrent_phy *cdns_phy,
static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
u32 num_lanes)
{
- u32 pwr_state = cdns_torrent_dp_read(cdns_phy,
+ struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
+ u32 pwr_state = cdns_torrent_dp_read(regmap,
PHY_PMA_XCVR_POWER_STATE_REQ);
- u32 pll_clk_en = cdns_torrent_dp_read(cdns_phy,
+ u32 pll_clk_en = cdns_torrent_dp_read(regmap,
PHY_PMA_XCVR_PLLCLK_EN);

/* Lane 0 is always enabled. */
@@ -628,9 +655,8 @@ static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
pll_clk_en &= ~(0x01U << 3);
}

- cdns_torrent_dp_write(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
- cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
+ cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
+ cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
}

/* Configure lane count as required. */
@@ -639,18 +665,19 @@ static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
{
u32 value;
u32 ret;
+ struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
u8 lane_mask = (1 << dp->lanes) - 1;

- value = cdns_torrent_dp_read(cdns_phy, PHY_RESET);
+ value = cdns_torrent_dp_read(regmap, PHY_RESET);
/* clear pma_tx_elec_idle_ln_* bits. */
value &= ~PMA_TX_ELEC_IDLE_MASK;
/* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
PMA_TX_ELEC_IDLE_MASK;
- cdns_torrent_dp_write(cdns_phy, PHY_RESET, value);
+ cdns_torrent_dp_write(regmap, PHY_RESET, value);

/* reset the link by asserting phy_l00_reset_n low */
- cdns_torrent_dp_write(cdns_phy, PHY_RESET,
+ cdns_torrent_dp_write(regmap, PHY_RESET,
value & (~PHY_L00_RESET_N_MASK));

/*
@@ -658,13 +685,13 @@ static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
* and powered down when re-enabling the link
*/
value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
- cdns_torrent_dp_write(cdns_phy, PHY_RESET, value);
+ cdns_torrent_dp_write(regmap, PHY_RESET, value);

cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);

/* release phy_l0*_reset_n based on used laneCount */
value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
- cdns_torrent_dp_write(cdns_phy, PHY_RESET, value);
+ cdns_torrent_dp_write(regmap, PHY_RESET, value);

/* Wait, until PHY gets ready after releasing PHY reset signal. */
ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
@@ -674,7 +701,7 @@ static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
ndelay(100);

/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
- cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
+ cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);

ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);

@@ -801,6 +828,7 @@ static int cdns_torrent_dp_init(struct phy *phy)
int ret;

struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
+ struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;

ret = clk_prepare_enable(cdns_phy->clk);
if (ret) {
@@ -825,7 +853,7 @@ static int cdns_torrent_dp_init(struct phy *phy)
return -EINVAL;
}

- cdns_torrent_dp_write(cdns_phy, PHY_AUX_CTRL, 0x0003); /* enable AUX */
+ cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */

/* PHY PMA registers configuration function */
cdns_torrent_dp_pma_cfg(cdns_phy);
@@ -841,11 +869,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
* used lanes
*/
lane_bits = (1 << cdns_phy->num_lanes) - 1;
- cdns_torrent_dp_write(cdns_phy, PHY_RESET,
+ cdns_torrent_dp_write(regmap, PHY_RESET,
((0xF & ~lane_bits) << 4) | (0xF & lane_bits));

/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
- cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
+ cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);

/* PHY PMA registers configuration functions */
/* Initialize PHY with max supported link rate, without SSC. */
@@ -861,7 +889,8 @@ static int cdns_torrent_dp_init(struct phy *phy)
cdns_phy->num_lanes);

/* take out of reset */
- cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1);
+ regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
+
ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
if (ret)
return ret;
@@ -884,10 +913,10 @@ int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
{
unsigned int reg;
int ret;
+ struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;

- ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, PHY_PMA_CMN_READY,
- reg, reg & 1, 0,
- POLL_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
+ reg & 1, 0, POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT) {
dev_err(cdns_phy->dev,
"timeout waiting for PMA common ready\n");
@@ -1405,6 +1434,7 @@ static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
u32 mask;
u32 read_val;
u32 ret;
+ struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;

switch (powerstate) {
case (POWERSTATE_A0):
@@ -1445,15 +1475,12 @@ static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
}

/* Set power state A<n>. */
- cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, value);
+ cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
/* Wait, until PHY acknowledges power state completion. */
- ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_ACK,
- read_val,
- (read_val & mask) == value, 0,
- POLL_TIMEOUT_US);
- cdns_torrent_dp_write(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
+ ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
+ read_val, (read_val & mask) == value, 0,
+ POLL_TIMEOUT_US);
+ cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
ndelay(100);

return ret;
@@ -1463,15 +1490,15 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
{
unsigned int read_val;
int ret;
+ struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;

/*
* waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
* master lane
*/
- ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
- PHY_PMA_XCVR_PLLCLK_EN_ACK,
- read_val, read_val & 1, 0,
- POLL_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
+ read_val, read_val & 1,
+ 0, POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT) {
dev_err(cdns_phy->dev,
"timeout waiting for link PLL clock enable ack\n");
@@ -1491,20 +1518,6 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
return ret;
}

-static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
- unsigned int offset,
- unsigned char start_bit,
- unsigned char num_bits,
- unsigned int val)
-{
- unsigned int read_val;
-
- read_val = cdns_torrent_dp_read(cdns_phy, offset);
- cdns_torrent_dp_write(cdns_phy, offset,
- ((val << start_bit) |
- (read_val & ~(((1 << num_bits) - 1) <<
- start_bit))));
-}

static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
u32 block_offset,
@@ -1554,6 +1567,14 @@ static int cdns_regfield_init(struct cdns_torrent_phy *cdns_phy)
}
cdns_phy->phy_pma_pll_raw_ctrl = field;

+ regmap = cdns_phy->regmap_dptx_phy_reg;
+ field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_RESET reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ cdns_phy->phy_reset_ctrl = field;
+
return 0;
}

@@ -1622,6 +1643,16 @@ static int cdns_regmap_init_torrent_dp(struct cdns_torrent_phy *cdns_phy,
}
cdns_phy->regmap_phy_pma_common_cdb = regmap;

+ block_offset = TORRENT_DPTX_PHY_OFFSET;
+ regmap = cdns_regmap_init(dev, base, block_offset,
+ reg_offset_shift,
+ &cdns_torrent_dptx_phy_config);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init DPTX PHY regmap\n");
+ return PTR_ERR(regmap);
+ }
+ cdns_phy->regmap_dptx_phy_reg = regmap;
+
return 0;
}

--
2.20.1

Next message: Yuti Amonkar: "[PATCH v4 10/13] phy: cadence-torrent: Use regmap to read and write Torrent PHY registers"
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