Re: [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver

[Vignesh Raghavendra]

On 25/02/20 11:54 am, Ramuthevar, Vadivel MuruganX wrote:
> Hi Rob,
> 
> ÂÂÂÂ Thank you for the review comments...
> 
> On 24/2/2020 11:54 PM, Rob Herring wrote:
>> On Tue, Feb 18, 2020 at 8:29 PM Ramuthevar,Vadivel MuruganX
>> <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote:
>>> From: Ramuthevar Vadivel Murugan
>>> <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx>
>> Cc the DT list if you want this reviewed.
> Sorry, next patch will add DT list in CC.
>>> Add dt-bindings documentation for Cadence-QSPI controller to support
>>> spi based flash memories.
>>>
>>> Signed-off-by: Ramuthevar Vadivel Murugan
>>> <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx>
>>> ---
>>> Â .../devicetree/bindings/spi/cdns,qspi-nor.yamlÂÂÂÂ | 147
>>> +++++++++++++++++++++
>>> Â 1 file changed, 147 insertions(+)
>>> Â create mode 100644
>>> Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>>> b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>>> new file mode 100644
>>> index 000000000000..1a4d6e8d0d0b
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>>> @@ -0,0 +1,147 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: "http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#";
>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#";
>>> +
>>> +title: Cadence QSPI Flash Controller support
>>> +
>>> +maintainers:
>>> +Â - Ramuthevar Vadivel Murugan
>>> <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx>
>>> +
>>> +allOf:
>>> +Â - $ref: "spi-controller.yaml#"
>>> +
>>> +description: |
>>> +Â Binding Documentation for Cadence QSPI controller,This controller is
>>> +Â present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver
>>> +Â has been tested On Intel's LGM SoC.
>>> +
>>> +Â - compatible : should be one of the following:
>>> +ÂÂÂÂÂÂÂ Generic default - "cdns,qspi-nor".
>>> +ÂÂÂÂÂÂÂ For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
>>> +ÂÂÂÂÂÂÂ For TI AM654 SoCÂ - "ti,am654-ospi", "cdns,qspi-nor".
>>> +ÂÂÂÂÂÂÂ For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
>>> +
>>> +properties:
>>> +Â compatible:
>>> +ÂÂÂ oneOf:
>>> +ÂÂÂÂÂ - items:
>>> +ÂÂÂÂÂÂÂ - enum:
>>> +ÂÂÂÂÂÂÂÂÂÂ - ti,k2g-qspi
>>> +ÂÂÂÂÂÂÂ - const: cdns,qspi-nor
>>> +
>>> +ÂÂÂÂÂ - items:
>>> +ÂÂÂÂÂÂÂ - enum:
>>> +ÂÂÂÂÂÂÂÂÂÂ - ti,am654-ospi
>>> +ÂÂÂÂÂÂÂ - const: cdns,qspi-nor
>>> +
>>> +ÂÂÂÂÂ - items:
>>> +ÂÂÂÂÂÂÂ - enum:
>>> +ÂÂÂÂÂÂÂÂÂÂ - intel,lgm-qspi
>>> +ÂÂÂÂÂÂÂ - const: cdns,qspi-nor
>>> +
>>> +ÂÂÂÂÂ - items:
>>> +ÂÂÂÂÂÂÂ - const: cdns,qspi-nor
>>> +
>>> +Â reg:
>>> +ÂÂÂ maxItems: 2
>>> +
>>> +Â interrupts:
>>> +ÂÂÂ maxItems: 1
>>> +
>>> +Â clocks:
>>> +ÂÂÂ maxItems: 1
>>> +
>>> +Â cdns,fifo-depth:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>>> +ÂÂÂ description:
>>> +ÂÂÂÂÂ Size of the data FIFO in words.
>> A 4GB fifo is valid? Add some constraints.
> 128 is valid, will update.


Nope, the width of this field is 8bits -> 256 bytes

>>> +
>>> +Â cdns,fifo-width:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>>> +ÂÂÂ description:
>>> +ÂÂÂÂÂ Bus width of the data FIFO in bytes.
>> Add some constraints.
> 4 is valid , will fix it.
>>> +
>>> +Â cdns,trigger-address:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>>> +ÂÂÂ description:
>>> +ÂÂÂÂÂ 32-bit indirect AHB trigger address.
>>> +
>>> +Â cdns,rclk-en:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>>> +ÂÂÂ description: |
>>> +ÂÂÂÂÂ Flag to indicate that QSPI return clock is used to latch the
>>> read data
>>> +ÂÂÂÂÂ rather than the QSPI clock. Make sure that QSPI return clock
>>> is populated
>>> +ÂÂÂÂÂ on the board before using this property.
>>> +
>>> +# subnode's properties
>>> +patternProperties:
>>> +Â "^.*@[0-9a-fA-F]+$":
>>> +ÂÂÂ type: object
>>> +ÂÂÂ description:
>>> +ÂÂÂÂÂ flash device uses the subnodes below defined properties.
>>> +
>>> +Â cdns,read-delay:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>>> +ÂÂÂ description:
>>> +ÂÂÂÂÂ Delay for read capture logic, in clock cycles.
>> 4 billion clock delay is valid?
> based on the ref_clk , will add it.
>>> +
>>> +Â cdns,tshsl-ns:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>> You can drop this, anything with a standard unit suffix already has a
>> type.
> sure , will drop it.
>>> +ÂÂÂ description: |
>>> +ÂÂÂÂÂ Delay in nanoseconds for the length that the master mode chip
>>> select
>>> +ÂÂÂÂÂ outputs are de-asserted between transactions.
>> Constraints...?
> 
> 50ns, will add it.
> 

This really depends on the input clk:

Clock Delay for Chip Select Deassert:

Delay in master reference clocks for the length that the master mode

chip select outputs are de-asserted between transactions The

minimum delay is always SCLK period to ensure the chip select is

never re-asserted within an SCLK period.

I don't see a easy way of verifying constraints in yaml.

Same applies for below 3 properties as well.

Regards
Vignesh

> Regards
> Vadivel
>>> +
>>> +Â cdns,tsd2d-ns:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>>> +ÂÂÂ description: |
>>> +ÂÂÂÂÂ Delay in nanoseconds between one chip select being de-activated
>>> +ÂÂÂÂÂ and the activation of another.
>>> +
>>> +Â cdns,tchsh-ns:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>>> +ÂÂÂ description: |
>>> +ÂÂÂÂÂ Delay in nanoseconds between last bit of current transaction and
>>> +ÂÂÂÂÂ deasserting the device chip select (qspi_n_ss_out).
>>> +
>>> +Â cdns,tslch-ns:
>>> +ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
>>> +ÂÂÂ description: |
>>> +ÂÂÂÂÂ Delay in nanoseconds between setting qspi_n_ss_out low and
>>> +ÂÂÂÂÂ first bit transfer.
>>> +
>>> +required:
>>> +Â - compatible
>>> +Â - reg
>>> +Â - interrupts
>>> +Â - clocks
>>> +Â - cdns,fifo-depth
>>> +Â - cdns,fifo-width
>>> +Â - cdns,trigger-address
>>> +
>>> +examples:
>>> +Â - |
>>> +ÂÂÂ qspi: spi@ff705000 {
>>> +ÂÂÂÂÂÂÂÂÂ compatible = "cdns,qspi-nor";
>>> +ÂÂÂÂÂÂÂÂÂ #address-cells = <1>;
>>> +ÂÂÂÂÂÂÂÂÂ #size-cells = <0>;
>>> +ÂÂÂÂÂÂÂÂÂ reg = <0xff705000 0x1000>,
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <0xffa00000 0x1000>;
>>> +ÂÂÂÂÂÂÂÂÂ interrupts = <0 151 4>;
>>> +ÂÂÂÂÂÂÂÂÂ clocks = <&qspi_clk>;
>>> +ÂÂÂÂÂÂÂÂÂ cdns,fifo-depth = <128>;
>>> +ÂÂÂÂÂÂÂÂÂ cdns,fifo-width = <4>;
>>> +ÂÂÂÂÂÂÂÂÂ cdns,trigger-address = <0x00000000>;
>>> +
>>> +ÂÂÂÂÂÂÂÂÂ flash0: n25q00@0 {
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ compatible = "jedec,spi-nor";
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ reg = <0x0>;
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ cdns,read-delay = <4>;
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ cdns,tshsl-ns = <50>;
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ cdns,tsd2d-ns = <50>;
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ cdns,tchsh-ns = <4>;
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ cdns,tslch-ns = <4>;
>>> +ÂÂÂÂÂÂÂÂÂ };
>>> +ÂÂÂ };
>>> +
>>> -- 
>>> 2.11.0
>>>

-- 
Regards
Vignesh