Agreed, Thanks!
On 25/02/20 1:08 pm, Ramuthevar, Vadivel MuruganX wrote:
This has nothing to do with quad-mode. Its about how much SRAM amount ofcorrect me if I am wrong, the width of this field is 4bits -> 128 bytesNope, the width of this field is 8bits -> 256 bytes128 is valid, will update.+A 4GB fifo is valid? Add some constraints.
+Â cdns,fifo-depth:
+ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32
+ÂÂÂ description:
+ÂÂÂÂÂ Size of the data FIFO in words.
(based on QUAD mode) .
SRAM is present to buffer INDAC mode data. For TI platforms this is 256
bytes.
See CQSPI_REG_SRAMPARTITION definition in your datasheet.