RE: [PATCH v2 09/14] ARM: imx: cpuidle-imx7ulp: Stop mode disallowed when HSRUN

[Peng Fan]

Hi Shawn,

> Subject: Re: [PATCH v2 09/14] ARM: imx: cpuidle-imx7ulp: Stop mode
> disallowed when HSRUN
> 
> On Wed, Feb 19, 2020 at 03:59:52PM +0800, peng.fan@xxxxxxx wrote:
> > From: Peng Fan <peng.fan@xxxxxxx>
> >
> > When cpu runs in HSRUN mode, cpuidle is not allowed to run into Stop
> > mode. So add imx7ulp_get_mode to get thr cpu run mode, and use WAIT
> > mode instead, when cpu in HSRUN mode.
> >
> > Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
> 
> Why do you have cpuidle patches in a series titled as adding cpufreq support?

The whole patchset is to add cpufreq support for i.MX7ULP.
But i.MX7ULP only support two freq points. One freq point is HSRUN point,
When cpu runs in this point, cpu is not allowed to run into STOP mode from
hardware perspective. Should I submit this patch as a standalone patch?

Thanks,
Peng.

> 
> Shawn
> 
> > ---
> >  arch/arm/mach-imx/common.h          |  1 +
> >  arch/arm/mach-imx/cpuidle-imx7ulp.c | 14 +++++++++++---
> >  arch/arm/mach-imx/pm-imx7ulp.c      | 10 ++++++++++
> >  3 files changed, 22 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/common.h
> b/arch/arm/mach-imx/common.h
> > index 5aa5796cff0e..db542da4fe67 100644
> > --- a/arch/arm/mach-imx/common.h
> > +++ b/arch/arm/mach-imx/common.h
> > @@ -104,6 +104,7 @@ void imx6_set_int_mem_clk_lpm(bool enable);
> void
> > imx6sl_set_wait_clk(bool enter);  int imx_mmdc_get_ddr_type(void);
> > int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
> > +u32 imx7ulp_get_mode(void);
> >
> >  void imx_cpu_die(unsigned int cpu);
> >  int imx_cpu_kill(unsigned int cpu);
> > diff --git a/arch/arm/mach-imx/cpuidle-imx7ulp.c
> > b/arch/arm/mach-imx/cpuidle-imx7ulp.c
> > index ca86c967d19e..e7009d10b331 100644
> > --- a/arch/arm/mach-imx/cpuidle-imx7ulp.c
> > +++ b/arch/arm/mach-imx/cpuidle-imx7ulp.c
> > @@ -15,10 +15,18 @@
> >  static int imx7ulp_enter_wait(struct cpuidle_device *dev,
> >  			    struct cpuidle_driver *drv, int index)  {
> > -	if (index == 1)
> > +	u32 mode;
> > +
> > +	if (index == 1) {
> >  		imx7ulp_set_lpm(ULP_PM_WAIT);
> > -	else
> > -		imx7ulp_set_lpm(ULP_PM_STOP);
> > +	} else {
> > +		mode = imx7ulp_get_mode();
> > +
> > +		if (mode == 3)
> > +			imx7ulp_set_lpm(ULP_PM_WAIT);
> > +		else
> > +			imx7ulp_set_lpm(ULP_PM_STOP);
> > +	}
> >
> >  	cpu_do_idle();
> >
> > diff --git a/arch/arm/mach-imx/pm-imx7ulp.c
> > b/arch/arm/mach-imx/pm-imx7ulp.c index 393faf1e8382..1410ccfc71bd
> > 100644
> > --- a/arch/arm/mach-imx/pm-imx7ulp.c
> > +++ b/arch/arm/mach-imx/pm-imx7ulp.c
> > @@ -63,6 +63,16 @@ int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode
> mode)
> >  	return 0;
> >  }
> >
> > +u32 imx7ulp_get_mode(void)
> > +{
> > +	u32 mode;
> > +
> > +	mode = readl_relaxed(smc1_base + SMC_PMCTRL) &
> BM_PMCTRL_RUNM;
> > +	mode >>= BP_PMCTRL_RUNM;
> > +
> > +	return mode;
> > +}
> > +
> >  void __init imx7ulp_pm_init(void)
> >  {
> >  	struct device_node *np;
> > --
> > 2.16.4
> >