[PATCH v2 0/5] PEBS virtualization enabling via Intel PT

[Luwei Kang]

Intel new hardware(Atom processors based on the Tremont
microarchitecture) introduces some Processor Event-Based Sampling(PEBS)
extensions that output the PEBS record to Intel PT stream instead of DS
area. The PEBS record will be packaged in a specific format when
outputting to Intel PT.

This patch set will enable PEBS functionality in KVM Guest by PEBS output
to Intel PT, base on PEBS virtualization enabling via DS patch set[1].

Compared to the v1, the common code of PEBS virtualization enabling(PEBS
via DS and PEBS via Intel PT) has been moved to PEBS via DS patch set.
This patch set only includes the PEBS via PT specific changes.

Patch 1 is an extension to get fixed function counter by reload MSRs;
Patch 2,3 implement the CPUID and MSRs emulation;
Patch 4 will add the counter reload MSRs to MSR list during VM-entry/exit;
Patch 5 will swith the PEBS records to Intel PT buffer if PEBS via PT is
        enabled in KVM guest.

[1]: https://lore.kernel.org/kvm/1583431025-19802-1-git-send-email-luwei.kang@xxxxxxxxx/

Luwei Kang (5):
  KVM: x86/pmu: Add base address parameter for get_fixed_pmc function
  KVM: x86/pmu: Expose PDCM feature when PEBS output to PT
  KVM: x86/pmu: PEBS output Intel PT MSRs emulation
  KVM: x86/pmu: Add counter reload register to MSR list
  KVM: VMX: Switch PEBS records output to Intel PT buffer

 arch/x86/events/perf_event.h     |   5 --
 arch/x86/include/asm/kvm_host.h  |   2 +
 arch/x86/include/asm/msr-index.h |   6 +++
 arch/x86/kvm/pmu.h               |   6 +--
 arch/x86/kvm/vmx/capabilities.h  |   9 +++-
 arch/x86/kvm/vmx/pmu_intel.c     | 112 ++++++++++++++++++++++++++++++++++-----
 arch/x86/kvm/vmx/vmx.c           |   3 ++
 arch/x86/kvm/vmx/vmx.h           |   2 +-
 arch/x86/kvm/x86.c               |  32 +++++++++++
 9 files changed, 154 insertions(+), 23 deletions(-)

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1.8.3.1