[PATCH v3 1/5] dt-bindings: phy: Document Samsung UFS PHY bindings

From: Alim Akhtar
Date: Thu Mar 19 2020 - 11:07:11 EST


This patch documents Samsung UFS PHY device tree bindings

Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
---
.../bindings/phy/samsung,ufs-phy.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
new file mode 100644
index 000000000000..df54129004e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series UFS PHY Device Tree Bindings
+
+maintainers:
+ - Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - samsung,exynos7-ufs-phy
+
+ reg:
+ maxItems: 1
+ description: PHY base register address
+
+ reg-names:
+ items:
+ - const: phy-pma
+
+ clocks:
+ items:
+ - description: PLL reference clock
+ - description: Referencec clock parrent
+
+ clock-names:
+ items:
+ - const: ref_clk_parent
+ - const: ref_clk
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos7-clk.h>
+
+ ufs_phy: ufs-phy@0x15571800 {
+ compatible = "samsung,exynos7-ufs-phy";
+ reg = <0x15571800 0x240>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&clock_fsys1 MOUT_FSYS1_PHYCLK_SEL1>,
+ <&clock_top1 CLK_SCLK_PHY_FSYS1_26M>;
+ clock-names = "ref_clk_parent",
+ "ref_clk";
+ };
+
+...

base-commit: fb33c6510d5595144d585aa194d377cf74d31911
--
2.17.1