Re: [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register

[Anshuman Khandual]

On 03/20/2020 11:37 PM, Suzuki K Poulose wrote:
> Cc: Mark Rutland

Sure, will add this to all the patches here. Also add 'Suggested-by'
tags on all the changes proposed by Mark. Should have already added
that in this version as well, my bad.

> 
> On 01/28/2020 12:39 PM, Anshuman Khandual wrote:
>> Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487E.a
>> specification. Except RAS and AMU, all other feature bits are now enabled.
>>
>> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
>> Cc: Will Deacon <will@xxxxxxxxxx>
>> Cc: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
>> Cc: linux-kernel@xxxxxxxxxxxxxxx
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
> 
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
> 
>> ---
>> Â arch/arm64/include/asm/sysreg.h | 3 +++
>>  arch/arm64/kernel/cpufeature.c | 2 ++
>> Â 2 files changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 054aab7ebf1b..469d61c8fabf 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -718,6 +718,9 @@
>> Â #define ID_ISAR6_DP_SHIFTÂÂÂÂÂÂÂ 4
>> Â #define ID_ISAR6_JSCVT_SHIFTÂÂÂÂÂÂÂ 0
>> Â +#define ID_PFR0_DIT_SHIFTÂÂÂÂÂÂÂ 24
>> +#define ID_PFR0_CSV2_SHIFTÂÂÂÂÂÂÂ 16
>> +
>> Â #define ID_PFR2_SSBS_SHIFTÂÂÂÂÂÂÂ 4
>> Â #define ID_PFR2_CSV3_SHIFTÂÂÂÂÂÂÂ 0
>> Â diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index c1e837fc8f97..9e4dab15c608 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -341,6 +341,8 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
>> Â };
>> Â Â static const struct arm64_ftr_bits ftr_id_pfr0[] = {
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
>> ÂÂÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),ÂÂÂÂÂÂÂ /* State3 */
>> ÂÂÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),ÂÂÂÂÂÂÂ /* State2 */
>> ÂÂÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),ÂÂÂÂÂÂÂ /* State1 */
>>
> 
>