Re: [PATCH 6/6] arm64/cpufeature: Replace all open bits shift encodings with macros

[Anshuman Khandual]

On 03/21/2020 12:10 AM, Suzuki K Poulose wrote:
> On 01/28/2020 12:39 PM, Anshuman Khandual wrote:
>> There are many open bits shift encodings for various CPU ID registers that
>> are scattered across cpufeature. This replaces them with register specific
>> sensible macro definitions. This should not have any functional change.
>>
>> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
>> Cc: Will Deacon <will@xxxxxxxxxx>
>> Cc: Marc Zyngier <maz@xxxxxxxxxx>
>> Cc: Mark Rutland <mark.rutland@xxxxxxx>
>> Cc: James Morse <james.morse@xxxxxxx>
>> Cc: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
>> Cc: linux-kernel@xxxxxxxxxxxxxxx
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
>> ---
> 
> 
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -263,7 +263,7 @@ static const struct arm64_ftr_bits ftr_ctr[] = {
>> ÂÂÂÂÂÂ * make use of *minLine.
>> ÂÂÂÂÂÂ * If we have differing I-cache policies, report it as the weakest - VIPT.
>> ÂÂÂÂÂÂ */
>> -ÂÂÂ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),ÂÂÂ /* L1Ip */
>> +ÂÂÂ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT),ÂÂÂ /* L1Ip */
>> ÂÂÂÂÂ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
>> ÂÂÂÂÂ ARM64_FTR_END,
>> Â };
>> @@ -274,19 +274,19 @@ struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
>> Â };
>> Â Â static const struct arm64_ftr_bits ftr_it will not be a good idea to id_mmfr0[] = {
>> -ÂÂÂ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),ÂÂÂ /* InnerShr */
>> -ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),ÂÂÂ /* FCSE */
>> -ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),ÂÂÂ /* AuxReg */
>> -ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),ÂÂÂ /* TCM */
>> -ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),ÂÂÂ /* ShareLvl */
>> -ÂÂÂ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),ÂÂÂ /* OuterShr */
>> -ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),ÂÂÂ /* PMSA */
>> -ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),ÂÂÂ /* VMSA */
>> +ÂÂÂ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
>> +ÂÂÂ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
>> ÂÂÂÂÂ ARM64_FTR_END,
>> Â };
>> Â Â static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
>> -ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DOUBLELOCK_SHIFT, 28, 0),
> 
> This must be a signed feature, as we have the following possible values :
> 
> ÂÂÂÂ0b0000 - Double lock implemented
> ÂÂÂÂ0b1111 - Double lock not implemented.
> 
> So, in case of a conflict we want the safe value as 0b1111.
> 
> Please could you fix this as well ?

Sure but in a separate patch, as would like to prevent mixing any
actual code change from macro replacement.

> 
> 
> This patch as such looks fine to me.
> 
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
>