Re: [patch v3 3/4] EDAC: synopsys: Add edac driver support for i.MX8MP

[Robert Richter]

On 02.04.20 09:06:27, Sherry Sun wrote:
> > From: Robert Richter <rrichter@xxxxxxxxxxx>
> > On 02.04.20 09:20:32, Sherry Sun wrote:

> > > +static void enable_intr_imx8mp(struct synps_edac_priv *priv) {
> > > +	int regval;
> > > +
> > > +	regval = readl(priv->baseaddr + ECC_CLR_OFST);
> > > +	regval |= (DDR_CE_INTR_EN_MASK | DDR_UE_INTR_EN_MASK);
> > > +	writel(regval, priv->baseaddr + ECC_CLR_OFST); }
> > > +
> > > +static void disable_intr_imx8mp(struct synps_edac_priv *priv) {
> > > +	int regval;
> > > +
> > > +	regval = readl(priv->baseaddr + ECC_CLR_OFST);
> > > +	regval &= ~(DDR_CE_INTR_EN_MASK | DDR_UE_INTR_EN_MASK);
> > > +	writel(regval, priv->baseaddr + ECC_CLR_OFST); }
> > > +
> > > +/* Interrupt Handler for ECC interrupts on imx8mp platform. */ static
> > > +irqreturn_t intr_handler_imx8mp(int irq, void *dev_id) {
> > > +	const struct synps_platform_data *p_data;
> > > +	struct mem_ctl_info *mci = dev_id;
> > > +	struct synps_edac_priv *priv;
> > > +	int status, regval;
> > > +
> > > +	priv = mci->pvt_info;
> > > +	p_data = priv->p_data;
> > > +
> > > +	regval = readl(priv->baseaddr + ECC_STAT_OFST);
> > > +	if (!(regval & ECC_INTR_MASK))
> > > +		return IRQ_NONE;
> > > +
> > > +	status = p_data->get_error_info(priv);
> > > +	if (status)
> > > +		return IRQ_NONE;
> > > +
> > > +	priv->ce_cnt += priv->stat.ce_cnt;
> > > +	priv->ue_cnt += priv->stat.ue_cnt;
> > > +	handle_error(mci, &priv->stat);
> > > +
> > > +	edac_dbg(3, "Total error count CE %d UE %d\n",
> > > +		 priv->ce_cnt, priv->ue_cnt);
> > > +	enable_intr_imx8mp(priv);
> > 
> > Why do you enable interrupts here?
> 
> Because zynqmp_get_error_info() wrote 0 to ECC_CLR_OFST, so here have to re-enable the interrupts.

This does not seem to be the right place for it.

> As said in the commit, the main difference between ZynqMP and i.MX8MP ddr controller is the interrupt registers.
> ZynqMP use DDR QOS Interrupt registers,  but i.MX8MP use ECC_CLR_OFST Register(bit8 and bit9) to enable/disable the ce/ue interrupts. 
> 
> In zynqmp_get_error_info(), Zynqmp wrote 0 to ECC_CLR_OFST register to clear CE/UE error flags and counts, it has no effect on Zynqmp interrupts. 
> But for i.MX8MP, wirte 0 to ECC_CLR_OFST will disable i.MX8MP CE/UE interrupt, so need re-enable the interrupts.

All this shows one more time there should be separate handlers. You
should get rid most callbacks in struct synps_platform_data and
instead have separate probe functions for both flavors that share
common code.

-Robert