Re: AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection

[Masami Hiramatsu]

On Tue, 7 Apr 2020 17:54:49 +0200
Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:

> On Wed, Apr 08, 2020 at 12:41:11AM +0900, Masami Hiramatsu wrote:
> > On Tue, 7 Apr 2020 13:15:35 +0200
> > Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> 
> > > > > Also, all the VMX bits seems to qualify as FPU (I can't remember seeing
> > > > > that previously):
> > > > 
> > > > Oops, let me check it.
> > > 
> > > I just send you another patch that could do with insn_is_vmx()
> > > (sorry!!!)
> > 
> > Hmm, it is hard to find out the vmx insns. Maybe we need to clarify it by
> > opcode pattern. (like "VM.*")
> 
> Yeah, I know. Maybe I should just keep it as I have for now.
> 
> One thing I thought of is we could perhaps add manual markers in
> x86-opcode-map.txt. The '{','}' characters appear unused so far, we
> perhaps we can use them to classify things.
> 
> That could maybe replace "mmx_expr" as well. That is, something like so:

Thanks for the good suggestion!
Maybe this is much better than the fragile mnemonic pattern matching :)

BTW, I would like to use {VIRT} instead of {VMX} because some
instructions are for SVM.

Thank you!

> 
> ---
> 
> diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
> index ec31f5b60323..e01b76e0a294 100644
> --- a/arch/x86/lib/x86-opcode-map.txt
> +++ b/arch/x86/lib/x86-opcode-map.txt
> @@ -462,9 +462,9 @@ AVXcode: 1
>  75: pcmpeqw Pq,Qq | vpcmpeqw Vx,Hx,Wx (66),(v1)
>  76: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1)
>  # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX.
> -77: emms | vzeroupper | vzeroall
> -78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev)
> -79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev)
> +77: emms {FPU} | vzeroupper | vzeroall
> +78: VMREAD Ey,Gy {VMX} | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev)
> +79: VMWRITE Gy,Ey {VMX} | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev)
>  7a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev)
>  7b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev)
>  7c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2)
> @@ -965,9 +965,9 @@ GrpTable: Grp6
>  EndTable
>  
>  GrpTable: Grp7
> -0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B)
> +0: SGDT Ms | VMCALL (001),(11B) {VMX} | VMLAUNCH (010),(11B) {VMX} | VMRESUME (011),(11B) {VMX} | VMXOFF (100),(11B) {VMX} | PCONFIG (101),(11B) | ENCLV (000),(11B)
>  1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B)
> -2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)
> +2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) {VMX} | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)
>  3: LIDT Ms
>  4: SMSW Mw/Rv
>  5: rdpkru (110),(11B) | wrpkru (111),(11B) | SAVEPREVSSP (F3),(010),(11B) | RSTORSSP Mq (F3) | SETSSBSY (F3),(000),(11B)
> @@ -987,8 +987,8 @@ GrpTable: Grp9
>  3: xrstors
>  4: xsavec
>  5: xsaves
> -6: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3) | RDRAND Rv (11B)
> -7: VMPTRST Mq | VMPTRST Mq (F3) | RDSEED Rv (11B)
> +6: VMPTRLD Mq {VMX} | VMCLEAR Mq (66) {VMX} | VMXON Mq (F3) {VMX} | RDRAND Rv (11B)
> +7: VMPTRST Mq {VMX} | VMPTRST Mq (F3) {VMX} | RDSEED Rv (11B)
>  EndTable
>  
>  GrpTable: Grp10
> @@ -1036,10 +1036,10 @@ GrpTable: Grp14
>  EndTable
>  
>  GrpTable: Grp15
> -0: fxsave | RDFSBASE Ry (F3),(11B)
> -1: fxstor | RDGSBASE Ry (F3),(11B)
> -2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)
> -3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
> +0: fxsave {FPU} | RDFSBASE Ry (F3),(11B)
> +1: fxrstor {FPU} | RDGSBASE Ry (F3),(11B)
> +2: ldmxcsr {FPU} | vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)
> +3: stmxcsr {FPU} | vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
>  4: XSAVE | ptwrite Ey (F3),(11B)
>  5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B)
>  6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3)


-- 
Masami Hiramatsu <mhiramat@xxxxxxxxxx>