Re: [PATCH] arm64: dts: mt8173: Add gce setting in mmsys and display node
From: Chun-Kuang Hu
Date: Wed Apr 08 2020 - 12:09:48 EST
Hi, Hsin-Yi:
Enric Balletbo Serra <eballetbo@xxxxxxxxx> æ 2020å4æ8æ éä äå11:48åéï
>
> Missatge de Hsin-Yi Wang <hsinyi@xxxxxxxxxxxx> del dia dl., 18 de nov.
> 2019 a les 11:43:
> >
> > In order to use GCE function, we need add some informations
> > into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> >
> > Signed-off-by: Hsin-Yi Wang <hsinyi@xxxxxxxxxxxx>
>
> With the fix provided by Hsin-Yi [1] and after the mmsys patches
> landed I get GCE function working on mt8173, so
>
> Tested-by: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx>
>
> [1] https://lore.kernel.org/lkml/20200406051131.225748-1-hsinyi@xxxxxxxxxxxx/
>
> Thanks,
> Enric
>
> > ---
> > - This is based on series "support gce on mt8183 platform"
> > https://patchwork.kernel.org/cover/11208309/
> > - gce setting in 8183:
> > https://patchwork.kernel.org/patch/11127105/
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 15f1842f6df3..e84ec3f95d81 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -911,6 +911,11 @@ mmsys: clock-controller@14000000 {
> > assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
> > assigned-clock-rates = <400000000>;
> > #clock-cells = <1>;
> > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
Because of patch [1], atomic_exec parameter should be removed.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20200408&id=19d8e335d58a961a7ed377e5e2e63664b92c0b9c
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> > + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> > + <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
Because of patch [2], these events should be moved to mutex node.
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v5.6&id=60fa8c13ab1a33b8b958efb1510ec2fd8a064bcc
Regards,
Chun-Kuang.
> > };
> >
> > mdp_rdma0: rdma@14001000 {
> > @@ -991,6 +996,7 @@ ovl0: ovl@1400c000 {
> > clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > iommus = <&iommu M4U_PORT_DISP_OVL0>;
> > mediatek,larb = <&larb0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> > };
> >
> > ovl1: ovl@1400d000 {
> > @@ -1001,6 +1007,7 @@ ovl1: ovl@1400d000 {
> > clocks = <&mmsys CLK_MM_DISP_OVL1>;
> > iommus = <&iommu M4U_PORT_DISP_OVL1>;
> > mediatek,larb = <&larb4>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> > };
> >
> > rdma0: rdma@1400e000 {
> > @@ -1011,6 +1018,7 @@ rdma0: rdma@1400e000 {
> > clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> > mediatek,larb = <&larb0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> > };
> >
> > rdma1: rdma@1400f000 {
> > @@ -1021,6 +1029,7 @@ rdma1: rdma@1400f000 {
> > clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> > mediatek,larb = <&larb4>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> > };
> >
> > rdma2: rdma@14010000 {
> > @@ -1031,6 +1040,7 @@ rdma2: rdma@14010000 {
> > clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> > iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> > mediatek,larb = <&larb4>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> > };
> >
> > wdma0: wdma@14011000 {
> > @@ -1041,6 +1051,7 @@ wdma0: wdma@14011000 {
> > clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> > iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> > mediatek,larb = <&larb0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> > };
> >
> > wdma1: wdma@14012000 {
> > @@ -1051,6 +1062,7 @@ wdma1: wdma@14012000 {
> > clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> > iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> > mediatek,larb = <&larb4>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> > };
> >
> > color0: color@14013000 {
> > @@ -1059,6 +1071,7 @@ color0: color@14013000 {
> > interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> > };
> >
> > color1: color@14014000 {
> > @@ -1067,6 +1080,7 @@ color1: color@14014000 {
> > interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> > };
> >
> > aal@14015000 {
> > @@ -1075,6 +1089,7 @@ aal@14015000 {
> > interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > clocks = <&mmsys CLK_MM_DISP_AAL>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> > };
> >
> > gamma@14016000 {
> > @@ -1083,6 +1098,7 @@ gamma@14016000 {
> > interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> > };
> >
> > merge@14017000 {
> > --
> > 2.24.0.432.g9d3f5f5b63-goog
> >
> >
> > _______________________________________________
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>
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