Re: [PATCH v2 2/2] soc: qcom: rpmh-rsc: Timeout after 1 second in write_tcs_reg_sync()

[Stephen Boyd]

Quoting Douglas Anderson (2020-04-14 13:10:16)
> diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
> index f988e9cc2c30..02fc114ffb4f 100644
> --- a/drivers/soc/qcom/rpmh-rsc.c
> +++ b/drivers/soc/qcom/rpmh-rsc.c
> @@ -174,12 +175,13 @@ static void write_tcs_reg(const struct rsc_drv *drv, int reg, int tcs_id,
>  static void write_tcs_reg_sync(const struct rsc_drv *drv, int reg, int tcs_id,
>                                u32 data)
>  {
> +       u32 new_data;
> +
>         writel(data, tcs_reg_addr(drv, reg, tcs_id));
> -       for (;;) {
> -               if (data == readl(tcs_reg_addr(drv, reg, tcs_id)))
> -                       break;
> -               udelay(1);
> -       }
> +       if (readl_poll_timeout_atomic(tcs_reg_addr(drv, reg, tcs_id), new_data,
> +                                     new_data == data, 1, USEC_PER_SEC))
> +               pr_err("%s: error writing %#x to %d:%d\n", drv->name,

Shouldn't the register be hex? That seems to be how the registers are
represented. But I guess tcs_id is decimal and can't be translated to be
meaningful enough to indicate which TCS it is like the sleep or wake
one.

> +                      data, tcs_id, reg);
>  }