Re: [PATCH v5 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
From: Sandeep Maheswaram (Temp)
Date: Wed Apr 15 2020 - 04:53:47 EST
Hi Rob,
Any suggestions to solve this error in assigned-clock-rates
Regards
Sandeep
On 4/6/2020 10:09 PM, Sandeep Maheswaram (Temp) wrote:
Hi Rob,
On 4/4/2020 10:47 PM, Rob Herring wrote:
On Thu, Mar 26, 2020 at 12:36:07PM +0530, Sandeep Maheswaram wrote:
Convert USB DWC3 bindings to DT schema format using json-schema.
Signed-off-by: Sandeep Maheswaram <sanm@xxxxxxxxxxxxxx>
---
 .../devicetree/bindings/usb/qcom,dwc3.txt | 104
--------------
 .../devicetree/bindings/usb/qcom,dwc3.yaml | 158
+++++++++++++++++++++
 2 files changed, 158 insertions(+), 104 deletions(-)
 delete mode 100644
Documentation/devicetree/bindings/usb/qcom,dwc3.txt
 create mode 100644
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
new file mode 100644
index 0000000..0f69475
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+Â - Manu Gautam <mgautam@xxxxxxxxxxxxxx>
+
+properties:
+Â compatible:
+ÂÂÂ items:
+ÂÂÂÂÂ - enum:
+ÂÂÂÂÂÂÂÂÂ - qcom,msm8996-dwc3
+ÂÂÂÂÂÂÂÂÂ - qcom,msm8998-dwc3
+ÂÂÂÂÂÂÂÂÂ - qcom,sdm845-dwc3
+ÂÂÂÂÂ - const: qcom,dwc3
+
+Â reg:
+ÂÂÂ description: Offset and length of register set for QSCRATCH
wrapper
+ÂÂÂ maxItems: 1
+
+Â "#address-cells":
+ÂÂÂ enum: [ 1, 2 ]
+
+Â "#size-cells":
+ÂÂÂ enum: [ 1, 2 ]
+
+Â power-domains:
+ÂÂÂ description: specifies a phandle to PM domain provider node
+ÂÂÂ maxItems: 1
+
+Â clocks:
+ÂÂÂ description:
+ÂÂÂÂÂ A list of phandle and clock-specifier pairs for the clocks
+ÂÂÂÂÂ listed in clock-names.
+ÂÂÂ items:
+ÂÂÂÂÂ - description: System Config NOC clock.
+ÂÂÂÂÂ - description: Master/Core clock, has to be >= 125 MHz
+ÂÂÂÂÂÂÂÂÂ for SS operation and >= 60MHz for HS operation.
+ÂÂÂÂÂ - description: System bus AXI clock.
+ÂÂÂÂÂ - description: Mock utmi clock needed for ITP/SOF generation
+ÂÂÂÂÂÂÂÂÂ in host mode. Its frequency should be 19.2MHz.
+ÂÂÂÂÂ - description: Sleep clock, used for wakeup when
+ÂÂÂÂÂÂÂÂÂ USB3 core goes into low power mode (U3).
+
+Â clock-names:
+ÂÂÂ items:
+ÂÂÂÂÂ - const: cfg_noc
+ÂÂÂÂÂ - const: core
+ÂÂÂÂÂ - const: iface
+ÂÂÂÂÂ - const: mock_utmi
+ÂÂÂÂÂ - const: sleep
+
+Â assigned-clocks:
+ÂÂÂ items:
+ÂÂÂÂÂ - description: Phandle and clock specifier of MOCK_UTMI_CLK.
+ÂÂÂÂÂ - description: Phandle and clock specifoer of MASTER_CLK.
+
+Â assigned-clock-rates:
+ÂÂÂ maxItems: 2
Need to drop this as it is redundant. Soon this will generate an error.
Will do in next version.
+ÂÂÂ items:
+ÂÂÂÂÂ - description: Must be 19.2MHz (19200000).
Sounds like a constraint:
- const: 19200000
+ÂÂÂÂÂ - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS
mode.
- minimum: 60000000
ÂÂ maximum: ?
Tried as below but facing errors
assigned-clock-rates:
ÂÂÂ items:
ÂÂÂÂÂ - const: 19200000
ÂÂÂÂÂ - minimum: 60000000
ÂÂÂÂÂÂÂ maximum: 150000000
Errors
linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates: Additional items are not allowed
([150000000] was unexpected)
linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates:0: [19200000] is too short
linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates: [[19200000], [150000000]] is too long
+
+Â resets:
+ÂÂÂ maxItems: 1
+
+Â interrupts:
+ÂÂÂ items:
+ÂÂÂÂÂ - description: The interrupt that is asserted
+ÂÂÂÂÂÂÂÂÂ when a wakeup event is received on USB2 bus.
+ÂÂÂÂÂ - description: The interrupt that is asserted
+ÂÂÂÂÂÂÂÂÂ when a wakeup event is received on USB3 bus.
+ÂÂÂÂÂ - description: Wakeup event on DM line.
+ÂÂÂÂÂ - description: Wakeup event on DP line.
+
+Â interrupt-names:
+ÂÂÂ items:
+ÂÂÂÂÂ - const: hs_phy_irq
+ÂÂÂÂÂ - const: ss_phy_irq
+ÂÂÂÂÂ - const: dm_hs_phy_irq
+ÂÂÂÂÂ - const: dp_hs_phy_irq
+
+Â qcom,select-utmi-as-pipe-clk:
+ÂÂÂ description:
+ÂÂÂÂÂ If present, disable USB3 pipe_clk requirement.
+ÂÂÂÂÂ Used when dwc3 operates without SSPHY and only
+ÂÂÂÂÂ HS/FS/LS modes are supported.
+ÂÂÂ type: boolean
+
+# Required child node:
+
+patternProperties:
+Â "^dwc3@[0-9a-f]+$":
+ÂÂÂ type: object
+ÂÂÂ description:
+ÂÂÂÂÂ A child node must exist to represent the core DWC3 IP block
+ÂÂÂÂÂ The content of the node is defined in dwc3.txt.
+
+required:
+Â - compatible
+Â - reg
+Â - "#address-cells"
+Â - "#size-cells"
+Â - power-domains
+Â - clocks
+Â - clock-names
+
+examples:
+Â - |
+ÂÂÂ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ÂÂÂ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ÂÂÂ #include <dt-bindings/interrupt-controller/irq.h>
+ÂÂÂ usb@a6f8800 {
+ÂÂÂÂÂÂÂ compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
+ÂÂÂÂÂÂÂ reg = <0 0x0a6f8800 0 0x400>;
+
+ÂÂÂÂÂÂÂ #address-cells = <2>;
+ÂÂÂÂÂÂÂ #size-cells = <2>;
+
+ÂÂÂÂÂÂÂ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+ÂÂÂÂÂÂÂ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "sleep";
+
+ÂÂÂÂÂÂÂ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ÂÂÂÂÂÂÂ assigned-clock-rates = <19200000>, <150000000>;
+
+ÂÂÂÂÂÂÂ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+ÂÂÂÂÂÂÂ interrupt-names = "hs_phy_irq", "ss_phy_irq",
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+ÂÂÂÂÂÂÂ power-domains = <&gcc USB30_PRIM_GDSC>;
+
+ÂÂÂÂÂÂÂ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ÂÂÂÂÂÂÂ dwc3@a600000 {
+ÂÂÂÂÂÂÂÂÂÂÂ compatible = "snps,dwc3";
+ÂÂÂÂÂÂÂÂÂÂÂ reg = <0 0x0a600000 0 0xcd00>;
You need 'ranges' in the parent for this address to be translatable.
Will add in next version.
+ÂÂÂÂÂÂÂÂÂÂÂ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ÂÂÂÂÂÂÂÂÂÂÂ iommus = <&apps_smmu 0x740 0>;
+ÂÂÂÂÂÂÂÂÂÂÂ snps,dis_u2_susphy_quirk;
+ÂÂÂÂÂÂÂÂÂÂÂ snps,dis_enblslpm_quirk;
+ÂÂÂÂÂÂÂÂÂÂÂ phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ÂÂÂÂÂÂÂÂÂÂÂ phy-names = "usb2-phy", "usb3-phy";
+ÂÂÂÂÂÂÂ };
+ÂÂÂ };
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation