Re: [PATCH v2 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC

[Ramuthevar, Vadivel MuruganX]

Hi Boris,
ÂÂÂ Thank you very much for the review comments and your time...

On 20/4/2020 4:29 pm, Boris Brezillon wrote:
> On Fri, 17 Apr 2020 16:21:47 +0800
> "Ramuthevar,Vadivel MuruganX"
> <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote:
>
> > +
> > +	res = devm_platform_ioremap_resource_byname(pdev, lgm_host->cs_name);
> > +	lgm_host->nandaddr_va = res;
> > +	nandaddr_pa = res->start;
> > +	if (IS_ERR(lgm_host->nandaddr_va))
> > +		return PTR_ERR(lgm_host->nandaddr_va);
> Hm, I didn't realize you needed the physical address for DMA transfers.
> Just use platform_get_resource_by_name()+devm_ioremap_resource() in
> that case.
Yes, you are right, needed the physical address for DMA transfers.
> > +
> > +	writel(LGM_BUSCON_CMULT_V4 | LGM_BUSCON_RECOVC(1) |
> > +	       LGM_BUSCON_HOLDC(1) | LGM_BUSCON_WAITRDC(2) |
> > +	       LGM_BUSCON_WAITWRC(2) | LGM_BUSCON_BCGEN_CS | LGM_BUSCON_ALEC |
> > +	       LGM_BUSCON_SETUP_EN, lgm_host->lgm_va + LGM_BUSCON(cs));
> I'm sure some the timings you hardcode here can be extracted from the
> NAND timings. Can you see if you can implement ->setup_data_interface()
> instead.

Yes, I have seen few of the drivers implemented 
->setup_data_interface(), Noted.

Regards
Vadivel