RE: [RFC PATCH v2 09/13] perf vendor events: Add JSON metrics for imx8mm DDR Perf

[Joakim Zhang]

> -----Original Message-----
> From: John Garry <john.garry@xxxxxxxxxx>
> Sent: 2020年4月20日 22:20
> To: Joakim Zhang <qiangqing.zhang@xxxxxxx>; peterz@xxxxxxxxxxxxx;
> mingo@xxxxxxxxxx; acme@xxxxxxxxxx; mark.rutland@xxxxxxx;
> alexander.shishkin@xxxxxxxxxxxxxxx; jolsa@xxxxxxxxxx;
> namhyung@xxxxxxxxxx; will@xxxxxxxxxx
> Cc: irogers@xxxxxxxxxx; ak@xxxxxxxxxxxxxxx; Linuxarm
> <linuxarm@xxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx; Zhangshaokun
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> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [RFC PATCH v2 09/13] perf vendor events: Add JSON metrics for
> imx8mm DDR Perf
> 
> On 20/04/2020 12:25, Joakim Zhang wrote:
> >>> imx8_ddr.write_cycles: 13153 1000495125 1000495125
> >>> #           time             counts unit events
> >>>        1.000476625              13153
> imx8_ddr.write_cycles
> >> #    205.5 MB  imx8mm_ddr_write.all
> >>> imx8_ddr.write_cycles: 3582 1000681375 1000681375
> >>>        2.001167750               3582
> imx8_ddr.write_cycles
> >> #     56.0 MB  imx8mm_ddr_write.all
> >>>
> >>> 8QM:
> >>> root@imx8qmmek:~# ./perf stat -v -a -I 1000 -M imx8qm_ddr_read.all
> >> Note: for this example, I don't know why you didn't use
> >> imx8mm_ddr_write.all, as for your 8MM test, so we can compare the same.
> > Yes, I use the imx8mm_ddr_write.all, I just re-name the metric, change
> nothing else.
> 
> Well it's hard to even keep up - let alone help -  when you're debugging QM
> support, which is not supported in this series (only MM is), and I don't know
> exactly what is in this JSON who have created (for QM).
> 
> For a start, the MM json will use "i.mx8mm" compat, which I figure should not
> work for QM. Please explain this.

For common events, cycles(event=0x00), read-cycles(event=0x2a), write-cycles(event=0x2b), read(event=0x35), write(event=0x38), all these events listed in file (tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json) are compatible for all i.MX8 DDR Perf, only AXI events are various from each SoC. These events tested okay for MX8MM and MX8QM.

Same situation, metrics listed in file (tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json) is also compatible for all i.MX8 DDR Perf, since metric expression only contains read-cycles(event=0x2a) and write-cycles(event=0x2b).

Generally speaking, now pmu events and metrics on your branch should support both MX8MM and MX8QM without any change, as long as they export "i.mx8mm" identifier.

As I mentioned before, pmu events tested okay for MX8MM and MX8QM. Metric also tested okay for MX8MM.
For MX8QM which has two HW PMU(ddr0/ddr1), metric can work, but it would add metric twice which I think if it is possible to improve it in your serials. 

I guess the root cause is that "imx8_ddr.read_cycles" contains two HW PMU events (imx8_ddr0/read-cycles/ and imx8_ddr1/read-cycles/) and metricgroup can't handle it at present.

8QM:
root@imx8qmmek:~# ./perf stat -v -a -I 1000 -M imx8mm_ddr_read.all 
Using CPUID 0x00000000410fd030
metric expr imx8_ddr.read_cycles * 4 * 4 for imx8mm_ddr_read.all 
found event imx8_ddr.read_cycles
metric expr imx8_ddr.read_cycles * 4 * 4 for imx8mm_ddr_read.all 
found event imx8_ddr.read_cycles
adding {imx8_ddr.read_cycles}:W,{imx8_ddr.read_cycles}:W
imx8_ddr.read_cycles -> imx8_ddr0/event=0x2a/
imx8_ddr.read_cycles -> imx8_ddr1/event=0x2a/
imx8_ddr.read_cycles -> imx8_ddr0/event=0x2a/
imx8_ddr.read_cycles -> imx8_ddr1/event=0x2a/
imx8_ddr.read_cycles: 22748 1000378750 1000378750
imx8_ddr.read_cycles: 24640 1000376625 1000376625
imx8_ddr.read_cycles: 22800 1000375125 1000375125
imx8_ddr.read_cycles: 24616 1000372625 1000372625
#           time             counts unit events
     1.000377250              47388      imx8_ddr.read_cycles      #    740.4 MB  imx8qm_ddr_read.all
     1.000377250              47416      imx8_ddr.read_cycles

Best Regards,
Joakim Zhang
> Thanks,
> John
> 
> >
> >>> Using CPUID 0x00000000410fd030
> >>> metric expr imx8_ddr.read_cycles * 4 * 4 for i