Re: [PATCH v7 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver

[Bjorn Helgaas]

On Thu, May 07, 2020 at 05:28:36PM +0530, Bharat Kumar Gogada wrote:
> - Add support for Versal CPM as Root Port.
> - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
>   block for CPM along with the integrated bridge can function
>   as PCIe Root Port.
> - Bridge error and legacy interrupts in Versal CPM are handled using
>   Versal CPM specific interrupt line.

> +static inline bool cpm_pcie_link_up(struct xilinx_cpm_pcie_port *port)
> +{
> +	return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) &
> +		XILINX_CPM_PCIE_REG_PSCR_LNKUP) ? 1 : 0;

Almost all of the *_link_up() functions return "int".  I don't know if
there's really any benefit to using "bool", but if you do, you should
probably return "true" or "false" instead of 1/0.

> +	port->irq_misc = platform_get_irq(pdev, 0);
> +	if (port->irq_misc <= 0) {

Use:

  if (port->irq_misc < 0) {

See https://lore.kernel.org/r/20200501224042.141366-3-helgaas@xxxxxxxxxx