Re: [PATCH V2 2/3] clk: vc5: Enable addition output configurations of the Versaclock

[Adam Ford]

On Tue, May 12, 2020 at 5:05 PM Rob Herring <robh@xxxxxxxxxx> wrote:
>
> On Sat, May 02, 2020 at 07:21:25AM -0500, Adam Ford wrote:
> > The existing driver is expecting the Versaclock to be pre-programmed,
> > and only sets the output frequency.  Unfortunately, not all devices
> > are pre-programmed, and the Versaclock chip has more options beyond
> > just the frequency.
> >
> > This patch enables the following additional features:
> >
> >    - Programmable voltage: 1.8V, 2.5V, or 3.3V
> >    - Slew Percentage of normal: 85%, 90%, or 100%
> >    - Output Type: LVPECL, CMOS, HCSL, or LVDS
> >
> > Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
>
>
> > diff --git a/include/dt-bindings/clk/versaclock.h b/include/dt-bindings/clk/versaclock.h
> > new file mode 100644
> > index 000000000000..c6a6a0946564
> > --- /dev/null
> > +++ b/include/dt-bindings/clk/versaclock.h
>
> Belongs in binding patch.

I can do that, but the binding patch will have to be applied before
the rest of the series, or the source won't build because it's
referencing the bindings.  Is that OK?

adam
>
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +
> > +/* This file defines field values used by the versaclock 6 family
> > + * for defining output type
> > + */
> > +
> > +#define VC5_LVPECL   0
> > +#define VC5_CMOS     1
> > +#define VC5_HCSL33   2
> > +#define VC5_LVDS     3
> > +#define VC5_CMOS2    4
> > +#define VC5_CMOSD    5
> > +#define VC5_HCSL25   6
> > --
> > 2.25.1
> >