Re: [PATCH] MIPS: update tlb even if pte entry has no change

[Sergei Shtylyov]

On 14.05.2020 5:17, Bibo Mao wrote:

> From: bibo mao <maobibo@xxxxxxxxxxx>
>
> If there are two threads reading the same memory and tlb miss happens,
> one thread fills pte entry, the other reads new pte value during page fault
> handling. PTE value may be updated before page faul, so the process need

   Fault.

> need update tlb still.
>
> Also this patch define flush_tlb_fix_spurious_fault as empty, since it not
> necessary to flush the page for all CPUs
>
> Signed-off-by: Bibo Mao <maobibo@xxxxxxxxxxx>
[...]

MBR, Sergei