Re: [PATCH v30 02/20] x86/cpufeatures: x86/msr: Intel SGX Launch Control hardware bits

[Jarkko Sakkinen]

On Wed, May 20, 2020 at 02:23:47PM +0200, Borislav Petkov wrote:
> 
> > Subject: Re: [PATCH v30 02/20] x86/cpufeatures: x86/msr: Intel SGX Launch Control hardware bits
> 							  ^
> 							Add
> 
> Needs a verb.

"x86/cpufeatures: x86/msr: Add Intel SGX Launch Control hardware bits"

> On Fri, May 15, 2020 at 03:43:52AM +0300, Jarkko Sakkinen wrote:
> > From: Sean Christopherson <sean.j.christopherson@xxxxxxxxx>
> > 
> > Add X86_FEATURE_SGX_LC, which informs whether or not the CPU supports SGX
> > Launch Control.
> > 
> > Add MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}, which when combined contain a
> > SHA256 hash of a 3072-bit RSA public key. SGX backed software packages, so
> > called enclaves, are always signed. All enclaves signed with the public key
> > are unconditionally allowed to initialize. [1]
> > 
> > Add FEATURE_CONTROL_SGX_LE_WR bit of the feature control MSR, which informs
> > whether the formentioned MSRs are writable or not. If the bit is off, the
> 
> "aforementioned"
> 
> > public key MSRs are read-only for the OS.

Thanks, fixed.

> Regards/Gruss,
>     Boris.

/Jarkko