Re: [PATCHv3 2/2] dt-bindings: arm: coresight: Add support to skip trace unit power up
From: Mathieu Poirier
Date: Thu May 21 2020 - 11:54:08 EST
On Fri, 15 May 2020 at 10:23, Sai Prakash Ranjan
<saiprakash.ranjan@xxxxxxxxxxxxxx> wrote:
>
> From: Tingwei Zhang <tingwei@xxxxxxxxxxxxxx>
>
> Add "qcom,skip-power-up" property to identify systems which can
> skip powering up of trace unit since they share the same power
> domain as their CPU core. This is required to identify such
> systems with hardware errata which stops the CPU watchdog counter
> when the power up bit is set (TRCPDCR.PU).
>
> Signed-off-by: Tingwei Zhang <tingwei@xxxxxxxxxxxxxx>
> Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@xxxxxxxxxxxxxx>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@xxxxxxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 846f6daae71b..e4b2eda0b53b 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -108,6 +108,13 @@ its hardware characteristcs.
> * arm,cp14: must be present if the system accesses ETM/PTM management
> registers via co-processor 14.
>
> + * qcom,skip-power-up: boolean. Indicates that an implementation can
> + skip powering up the trace unit. TRCPDCR.PU does not have to be set
> + on Qualcomm Technologies Inc. systems since ETMs are in the same power
> + domain as their CPU cores. This property is required to identify such
> + systems with hardware errata where the CPU watchdog counter is stopped
> + when TRCPDCR.PU is set.
> +
> * Optional property for TMC:
Reviewed-by: Mathieu Poirier <mathieu.poirier@xxxxxxxxxx>
>
> * arm,buffer-size: size of contiguous buffer space for TMC ETR
> --
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