Re: [PATCH v4 07/13] mips: Add CONFIG/CONFIG6/Cause reg fields macro

[Thomas Bogendoerfer]

On Thu, May 21, 2020 at 05:07:18PM +0300, Serge Semin wrote:
> There are bit fields which persist in the MIPS CONFIG and CONFIG6
> registers, but haven't been described in the generic mipsregs.h
> header so far. In particular, the generic CONFIG bitfields are
> BE - endian mode, BM - burst mode, SB - SimpleBE, OCP interface mode
> indicator, UDI - user-defined "CorExtend" instructions, DSP - data
> scratch pad RAM present, ISP - instruction scratch pad RAM present,
> etc. The core-specific CONFIG6 bitfields are JRCD - jump register
> cache prediction disable, R6 - MIPSr6 extensions enable, IFUPerfCtl -
> IFU performance control, SPCD - sleep state performance counter, DLSB -
> disable load/store bonding. A new exception code reported in the
> ExcCode field of the Cause register: 30 - Parity/ECC error exception
> happened on either fetch, load or cache refill. Lets add them to the
> mipsregs.h header to be used in future platform code, which have them
> utilized.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
> Cc: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx>
> Cc: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>
> Cc: Paul Burton <paulburton@xxxxxxxxxx>
> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
> Cc: Arnd Bergmann <arnd@xxxxxxxx>
> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> ---
>  arch/mips/include/asm/mipsregs.h | 19 +++++++++++++++++++
>  arch/mips/kernel/spram.c         |  4 ++--
>  2 files changed, 21 insertions(+), 2 deletions(-)

applied to mips-next.

Thomas.

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