Re: [PATCH v4 06/13] mips: Add CP0 Write Merge config support

[Thomas Bogendoerfer]

On Thu, May 21, 2020 at 05:07:17PM +0300, Serge Semin wrote:
> CP0 config register may indicate whether write-through merging
> is allowed. Currently there are two types of the merging available:
> SysAD Valid and Full modes. Whether each of them are supported by
> the core is implementation dependent. Moreover whether the ability
> to change the mode also depends on the chip family instance. Taking
> into account all of this we created a dedicated mm_config() method
> to detect and enable merging if it's supported. It is called for
> MIPS-type processors at CPU-probe stage and attempts to detect whether
> the write merging is available. If it's known to be supported and
> switchable, then switch on the full mode. Otherwise just perform the
> CP0.Config.MM field analysis.
> 
> In addition there are platforms like InterAptiv/ProAptiv, which do have
> the MM bit field set by default, but having write-through cacheing
> unsupported makes write-merging also unsupported. In this case we just
> ignore the MM field value.
> 
> Co-developed-by: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Alexey Malahov <Alexey.Malahov@xxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
> Cc: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>
> Cc: Paul Burton <paulburton@xxxxxxxxxx>
> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
> Cc: Arnd Bergmann <arnd@xxxxxxxx>
> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> ---
>  arch/mips/include/asm/cpu-features.h |  8 +++++
>  arch/mips/include/asm/cpu.h          |  4 ++-
>  arch/mips/include/asm/mipsregs.h     |  3 ++
>  arch/mips/kernel/cpu-probe.c         | 48 ++++++++++++++++++++++++++++
>  4 files changed, 62 insertions(+), 1 deletion(-)

applied to mips-next.

Thomas.

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