Re: [PATCH V4 12/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register

[Anshuman Khandual]

On 05/19/2020 07:02 PM, Suzuki K Poulose wrote:
> On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
>> Enable EVC, FGT, EXS, TGRAN4_2, TGRAN64_2 and TGRAN16_2 features bits in
>> ID_AA64MMFR0 register as per ARM DDI 0487F.a specification.
>>
>> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
>> Cc: Will Deacon <will@xxxxxxxxxx>
>> Cc: Mark Rutland <mark.rutland@xxxxxxx>
>> Cc: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
>> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
>> Cc: linux-kernel@xxxxxxxxxxxxxxx
>>
>> Suggested-by: Will Deacon <will@xxxxxxxxxx>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
> 
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index d1433f996710..7ce19f97ba73 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -267,6 +267,10 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
>> Â };
>> Â Â static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
>> +
> 
> minor nit: spurious new line.
> 
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
>> +ÂÂÂ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
>> ÂÂÂÂÂ /*
>> ÂÂÂÂÂÂ * We already refuse to boot CPUs that don't support our configured
>> ÂÂÂÂÂÂ * page size, so we can only detect mismatches for a page size other
>> @@ -274,6 +278,9 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
>> ÂÂÂÂÂÂ * exist in the wild so, even though we don't like it, we'll have to go
>> ÂÂÂÂÂÂ * along with it and treat them as non-strict.
>> ÂÂÂÂÂÂ */
>> +ÂÂÂ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, ID_AA64MMFR0_TGRAN4_2_NI),
>> +ÂÂÂ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, ID_AA64MMFR0_TGRAN64_2_NI),
>> +ÂÂÂ S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, ID_AA64MMFR0_TGRAN16_2_NI),
> 
> These are not SIGNED as they don't have 0b1111 defined to represent
> something "lower" than '0b0'. It was signed for 4K and 64K, since
> 
> 0b0000 => supported
> 0b1111 => Not supported.
> 
> Also Please note, KVM-NV patches are adding these, so you may as well drop them.

Sure, will drop all ID_AA64MMFR0_TGRAN changes along with related
macros from arch/arm64/include/asm/sysreg.h.