Re: [PATCH 7/8] riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo

[Alex Ghiti]

Hi Anup,

Le 5/25/20 Ã 2:21 AM, Anup Patel a ÃcritÂ:
> On Sun, May 24, 2020 at 2:47 PM Alexandre Ghiti <alex@xxxxxxxx> wrote:
> > Now that the mmu type is determined at runtime using SATP
> > characteristic, use the global variable pgtable_l4_enabled to output
> > mmu type of the processor through /proc/cpuinfo instead of relying on
> > device tree infos.
> >
> > Signed-off-by: Alexandre Ghiti <alex@xxxxxxxx>
> > Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx>
> > Reviewed-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx>
> > ---
> >   arch/riscv/boot/dts/sifive/fu540-c000.dtsi |  4 ----
> >   arch/riscv/kernel/cpu.c                    | 24 ++++++++++++----------
> >   2 files changed, 13 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > index 7db861053483..6138590a2229 100644
> > --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > @@ -50,7 +50,6 @@
> >                          i-cache-size = <32768>;
> >                          i-tlb-sets = <1>;
> >                          i-tlb-size = <32>;
> > -                       mmu-type = "riscv,sv39";
> >                          reg = <1>;
> >                          riscv,isa = "rv64imafdc";
> >                          tlb-split;
> > @@ -74,7 +73,6 @@
> >                          i-cache-size = <32768>;
> >                          i-tlb-sets = <1>;
> >                          i-tlb-size = <32>;
> > -                       mmu-type = "riscv,sv39";
> >                          reg = <2>;
> >                          riscv,isa = "rv64imafdc";
> >                          tlb-split;
> > @@ -98,7 +96,6 @@
> >                          i-cache-size = <32768>;
> >                          i-tlb-sets = <1>;
> >                          i-tlb-size = <32>;
> > -                       mmu-type = "riscv,sv39";
> >                          reg = <3>;
> >                          riscv,isa = "rv64imafdc";
> >                          tlb-split;
> > @@ -122,7 +119,6 @@
> >                          i-cache-size = <32768>;
> >                          i-tlb-sets = <1>;
> >                          i-tlb-size = <32>;
> > -                       mmu-type = "riscv,sv39";
> >                          reg = <4>;
> >                          riscv,isa = "rv64imafdc";
> >                          tlb-split;
> Your PATCH6 is already doing the right thing by skipping CPU DT
> nodes that don't have "mmu-type" DT property.
>
> The "mmu-type" DT property is very critical for RUNTIME M-mode
> firmware (OpenSBI) because it tells whether a given CPU has MMU
> (or not). This is also in agreement with the current DT bindings
> document for RISC-V CPUs.
>
> I suggest to drop the change in sifive/fu540-c000.dtsi and rest of
> the patch is fine so my Reviewed-by still holds.


Ok I'll do that in v2, thanks.


Alex


> Regards,
> Anup
>
> > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> > index 40a3c442ac5f..38a699b997a8 100644
> > --- a/arch/riscv/kernel/cpu.c
> > +++ b/arch/riscv/kernel/cpu.c
> > @@ -8,6 +8,8 @@
> >   #include <linux/of.h>
> >   #include <asm/smp.h>
> >
> > +extern bool pgtable_l4_enabled;
> > +
> >   /*
> >    * Returns the hart ID of the given device tree node, or -ENODEV if the node
> >    * isn't an enabled and valid RISC-V hart node.
> > @@ -54,18 +56,19 @@ static void print_isa(struct seq_file *f, const char *isa)
> >          seq_puts(f, "\n");
> >   }
> >
> > -static void print_mmu(struct seq_file *f, const char *mmu_type)
> > +static void print_mmu(struct seq_file *f)
> >   {
> > +       char sv_type[16];
> > +
> >   #if defined(CONFIG_32BIT)
> > -       if (strcmp(mmu_type, "riscv,sv32") != 0)
> > -               return;
> > +       strncpy(sv_type, "sv32", 5);
> >   #elif defined(CONFIG_64BIT)
> > -       if (strcmp(mmu_type, "riscv,sv39") != 0 &&
> > -           strcmp(mmu_type, "riscv,sv48") != 0)
> > -               return;
> > +       if (pgtable_l4_enabled)
> > +               strncpy(sv_type, "sv48", 5);
> > +       else
> > +               strncpy(sv_type, "sv39", 5);
> >   #endif
> > -
> > -       seq_printf(f, "mmu\t\t: %s\n", mmu_type+6);
> > +       seq_printf(f, "mmu\t\t: %s\n", sv_type);
> >   }
> >
> >   static void *c_start(struct seq_file *m, loff_t *pos)
> > @@ -90,14 +93,13 @@ static int c_show(struct seq_file *m, void *v)
> >   {
> >          unsigned long cpu_id = (unsigned long)v - 1;
> >          struct device_node *node = of_get_cpu_node(cpu_id, NULL);
> > -       const char *compat, *isa, *mmu;
> > +       const char *compat, *isa;
> >
> >          seq_printf(m, "processor\t: %lu\n", cpu_id);
> >          seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
> >          if (!of_property_read_string(node, "riscv,isa", &isa))
> >                  print_isa(m, isa);
> > -       if (!of_property_read_string(node, "mmu-type", &mmu))
> > -               print_mmu(m, mmu);
> > +       print_mmu(m);
> >          if (!of_property_read_string(node, "compatible", &compat)
> >              && strcmp(compat, "riscv"))
> >                  seq_printf(m, "uarch\t\t: %s\n", compat);
> > --
> > 2.20.1