Re: [PATCH v2 2/2] drivers: clk: zynqmp: Update fraction clock check from custom type flags

[Stephen Boyd]

Quoting Jolly Shah (2020-03-12 14:31:39)
> From: Tejas Patel <tejas.patel@xxxxxxxxxx>
> 
> Older firmware version sets BIT(13) in clkflag to mark a
> divider as fractional divider. Updated firmware version sets BIT(4)
> in type flags to mark a divider as fractional divider since
> BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk
> framework flags.
> 
> To support both old and new firmware version, consider BIT(13) from
> clkflag and BIT(4) from type_flag to check if divider is fractional
> or not.
> 
> To maintain compatibility BIT(13) of clkflag in firmware will not be
> used in future for any purpose and will be marked as unused.
> 
> Signed-off-by: Tejas Patel <tejas.patel@xxxxxxxxxx>
> Signed-off-by: Rajan Vaja <rajan.vaja@xxxxxxxxxx>
> Signed-off-by: Jolly Shah <jolly.shah@xxxxxxxxxx>
> ---

Applied to clk-next