Re: [PATCH v3 01/13] clk: mmp: frac: Do not lose last 4 digits of precision

From: Stephen Boyd
Date: Wed May 27 2020 - 21:01:04 EST

Quoting Lubomir Rintel (2020-05-19 15:41:39)
> While calculating the output rate of a fractional divider clock, the
> value is divided and multipled by 10000, discarding the least
> significant digits -- presumably to fit the intermediate value within 32
> bits.
> The precision we're losing is, however, not insignificant for things like
> I2S clock. Maybe also elsewhere, now that since commit ea56ad60260e ("clk:
> mmp2: Stop pretending PLL outputs are constant") the parent rates are more
> precise and no longer rounded to 10000s.
> Signed-off-by: Lubomir Rintel <lkundrak@xxxxx>
> ---

Applied to clk-next