On 6/2/2020 4:10 PM, Dan Murphy wrote:
FlorianThose properties have a standard name, which makes them suitable for
On 6/2/20 5:33 PM, Florian Fainelli wrote:
On 6/2/2020 9:45 AM, Dan Murphy wrote:Why would we do that for these properties and not any other?
Add RGMII internal delay configuration for Rx and Tx.[snip]
Signed-off-by: Dan Murphy <dmurphy@xxxxxx>
---
+It is still not clear to me why is not the parsing being done by the PHY
 enum {
ÂÂÂÂÂ DP83869_PORT_MIRRORING_KEEP,
ÂÂÂÂÂ DP83869_PORT_MIRRORING_EN,
@@ -108,6 +113,8 @@ enum {
 struct dp83869_private {
ÂÂÂÂÂ int tx_fifo_depth;
ÂÂÂÂÂ int rx_fifo_depth;
+ÂÂÂ s32 rx_id_delay;
+ÂÂÂ s32 tx_id_delay;
ÂÂÂÂÂ int io_impedance;
ÂÂÂÂÂ int port_mirroring;
ÂÂÂÂÂ bool rxctrl_strap_quirk;
@@ -232,6 +239,22 @@ static int dp83869_of_init(struct phy_device
*phydev)
ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &dp83869->tx_fifo_depth))
ÂÂÂÂÂÂÂÂÂ dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
 + ret = of_property_read_u32(of_node, "rx-internal-delay-ps",
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &dp83869->rx_id_delay);
+ÂÂÂ if (ret) {
+ÂÂÂÂÂÂÂ dp83869->rx_id_delay =
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
+ÂÂÂÂÂÂÂ ret = 0;
+ÂÂÂ }
+
+ÂÂÂ ret = of_property_read_u32(of_node, "tx-internal-delay-ps",
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ &dp83869->tx_id_delay);
+ÂÂÂ if (ret) {
+ÂÂÂÂÂÂÂ dp83869->tx_id_delay =
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
+ÂÂÂÂÂÂÂ ret = 0;
+ÂÂÂ }
library helper directly?
parsing by the core PHY library.
Unless there is a new precedence being set here by having the PHYYou could parse the vendor properties through the driver, let the PHY
framework do all the dt node parsing for common properties.
library parse the standard properties, and resolve any ordering
precedence within the driver. In general, I would favor standard
properties over vendor properties.
Does this help?