Re: [PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU

[Chen-Yu Tsai]

On Wed, Jun 3, 2020 at 5:42 PM ææé <frank@xxxxxxxxxxxxxxxxx> wrote:
>
> >> + /* Enable the lock bits on all PLLs */
> >> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
> >> +  val = readl(reg + pll_regs[i]);
> >> +  val |= BIT(29);
> >
> >Having a define for that would be nice here
> >
> >> +  writel(val, reg + pll_regs[i]);
> >> + }
> >> +
> >> + /*
> >> +  * In order to pass the EMI certification, the SDM function of
> >> +  * the peripheral 1 bus is enabled, and the frequency is still
> >> +  * calculated using the previous division factor.
> >> +  */
> >> + writel(0xd1303333, reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG);
> >
> >Same here
>
> Having a define? I donât quite understand what you mean,
> can you give me an example?

What Maxime means is that 0xd1303333 is a magic number.
It is better to make a properly named macro, or many macros
that you then bitwise-OR together. So you should make macros
for each bitfield in that register, which would likely include
the SDM calculation factors, the enable bit, and any other fields.

ChenYu

> MBR,
> Yangtao