Re: [PATCH v5 07/11] PCI: qcom: Define some PARF params needed for ipq8064 SoC

[Stanimir Varbanov]

Hi,

On 6/2/20 2:53 PM, Ansuel Smith wrote:
> Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
> needed on some ipq8064 based device (Netgear R7800 for example). Without
> this the system locks on kernel load.
> 
> Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
> Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx # v4.5+
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index f2ea1ab6f584..f5398b0d270c 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -46,6 +46,9 @@
>  
>  #define PCIE20_PARF_PHY_CTRL			0x40
>  #define PCIE20_PARF_PHY_REFCLK			0x4C
> +#define PHY_REFCLK_SSP_EN			BIT(16)
> +#define PHY_REFCLK_USE_PAD			BIT(12)

These two are not used in the patch, please move it in 08/11.

> +
>  #define PCIE20_PARF_DBI_BASE_ADDR		0x168
>  #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
>  #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174
> @@ -77,6 +80,18 @@
>  #define DBI_RO_WR_EN				1
>  
>  #define PERST_DELAY_US				1000
> +/* PARF registers */
> +#define PCIE20_PARF_PCS_DEEMPH			0x34
> +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		((x) << 16)
> +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	((x) << 8)
> +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	((x) << 0)
> +
> +#define PCIE20_PARF_PCS_SWING			0x38
> +#define PCS_SWING_TX_SWING_FULL(x)		((x) << 8)
> +#define PCS_SWING_TX_SWING_LOW(x)		((x) << 0)
> +
> +#define PCIE20_PARF_CONFIG_BITS		0x50
> +#define PHY_RX0_EQ(x)				((x) << 24)
>  
>  #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
>  #define SLV_ADDR_SPACE_SZ			0x10000000
> @@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
>  	struct dw_pcie *pci = pcie->pci;
>  	struct device *dev = pci->dev;
> +	struct device_node *node = dev->of_node;
>  	u32 val;
>  	int ret;
>  
> @@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  	val &= ~BIT(0);
>  	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
>  
> +	if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
> +		writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
> +			       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
> +			       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
> +		       pcie->parf + PCIE20_PARF_PCS_DEEMPH);
> +		writel(PCS_SWING_TX_SWING_FULL(120) |
> +			       PCS_SWING_TX_SWING_LOW(120),
> +		       pcie->parf + PCIE20_PARF_PCS_SWING);

Please fix the indentations above.

> +		writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
> +	}
> +
>  	/* enable external reference clock */
>  	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
>  	val |= BIT(16);
> 

-- 
regards,
Stan