[PATCH] arm64: dts: odroid: add spicc0 controller node

[Hyeonki Hong]

Add enabled spicc0 controller node with annotations describing the
physical SPI0 pin number based on the 40 pin header on the Odroid
board.

Signed-off-by: Hyeonki Hong <hhk7734@xxxxxxxxx>
---
 .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 26 +++++++++++++++++--
 .../boot/dts/amlogic/meson-sm1-odroid-c4.dts  | 24 ++++++++++++++++-
 2 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
index 169ea283d4ee..ec6d345caaae 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
@@ -16,8 +16,9 @@
 	model = "Hardkernel ODROID-N2";
 
 	aliases {
-		serial0 = &uart_AO;
 		ethernet0 = &ethmac;
+		serial0 = &uart_AO;
+		spi0 = &spicc0
 	};
 
 	chosen {
@@ -328,7 +329,7 @@
 
 &ext_mdio {
 	external_phy: ethernet-phy@0 {
-		/* Realtek RTL8211F (0x001cc916) */	
+		/* Realtek RTL8211F (0x001cc916) */
 		reg = <0>;
 		max-speed = <1000>;
 
@@ -451,6 +452,27 @@
 	vqmmc-supply = <&flash_1v8>;
 };
 
+&spicc0 {
+	status = "okay";
+
+	/*
+	 * 40 Pin Header : MOSI(GPIOX.8->19 Pin),
+	 *		   MISO(GPIOX.9->21 Pin),
+	 *		   SPI0_CLK(GPIOX.11->23 Pin)
+	 *		   SPI_CE0(GPIOX.10->24 Pin),
+	 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>;
+
+	spidev@0 {
+		compatible = "spidev";
+		status = "okay";
+		/* spi default max clock 100Mhz */
+		spi-max-frequency = <100000000>;
+		reg = <0>;
+	};
+};
+
 /*
  * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
  * and eMMC Data 4 to 7 pins.
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
index 00d90b30f8b4..f809b2ba6b15 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts
@@ -14,8 +14,9 @@
 	model = "Hardkernel ODROID-C4";
 
 	aliases {
-		serial0 = &uart_AO;
 		ethernet0 = &ethmac;
+		serial0 = &uart_AO;
+		spi0 = &spicc0;
 	};
 
 	chosen {
@@ -381,6 +382,27 @@
 	vqmmc-supply = <&flash_1v8>;
 };
 
+&spicc0 {
+	status = "okay";
+
+	/*
+	 * 40 Pin Header : MOSI(GPIOX.8->19 Pin),
+	 *		   MISO(GPIOX.9->21 Pin),
+	 *		   SPI0_CLK(GPIOX.11->23 Pin)
+	 *		   SPI_CE0(GPIOX.10->24 Pin),
+	 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>;
+
+	spidev@0 {
+		compatible = "spidev";
+		status = "okay";
+		/* spi default max clock 100Mhz */
+		spi-max-frequency = <100000000>;
+		reg = <0>;
+	};
+};
+
 &uart_AO {
 	status = "okay";
 	pinctrl-0 = <&uart_ao_a_pins>;
-- 
2.17.1