Re: [PATCH 2/2] clocksource: Ingenic: Add support for the Ingenic X1000 OST.

From: kernel test robot
Date: Thu Jun 25 2020 - 07:01:23 EST

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In reply to: kernel test robot: "Re: [PATCH 2/2] clocksource: Ingenic: Add support for the Ingenic X1000 OST."
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Hi "åçæ,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on tip/timers/core]
[also build test WARNING on linux/master robh/for-next linus/master v5.8-rc2 next-20200624]
[cannot apply to daniel.lezcano/clockevents/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-support-for-the-OST-in-Ingenic-X1000/20200625-005621
base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 809eb4e9bf9d84eb5b703358afd0d564d514f6d2
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 1d4c87335d5236ea1f35937e1014980ba961ae34)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

>> drivers/clocksource/ingenic-sysost.c:221:9: warning: implicit conversion from 'unsigned long' to 'unsigned int' changes value from 18446744073709551614 to 4294967294 [-Wconstant-conversion]
writel(~OSTFR_FFLAG, ost->base + OST_REG_OSTFR);
~~~~~~ ^~~~~~~~~~~~
drivers/clocksource/ingenic-sysost.c:225:9: warning: implicit conversion from 'unsigned long' to 'unsigned int' changes value from 18446744073709551614 to 4294967294 [-Wconstant-conversion]
writel(~OSTMR_FMASK, ost->base + OST_REG_OSTMR);
~~~~~~ ^~~~~~~~~~~~
>> drivers/clocksource/ingenic-sysost.c:408:6: warning: variable 'ret' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
if (!ost->base) {
^~~~~~~~~~
drivers/clocksource/ingenic-sysost.c:469:9: note: uninitialized use occurs here
return ret;
^~~
drivers/clocksource/ingenic-sysost.c:408:2: note: remove the 'if' if its condition is always false
if (!ost->base) {
^~~~~~~~~~~~~~~~~
drivers/clocksource/ingenic-sysost.c:401:9: note: initialize the variable 'ret' to silence this warning
int ret;
^
= 0
3 warnings generated.

vim +221 drivers/clocksource/ingenic-sysost.c

215
216 static int ingenic_ost_cevt_set_next(unsigned long next,
217 struct clock_event_device *evt)
218 {
219 struct ingenic_ost *ost = to_ingenic_ost(evt);
220
> 221 writel(~OSTFR_FFLAG, ost->base + OST_REG_OSTFR);
222 writel(next, ost->base + OST_REG_OST1DFR);
223 writel(OSTCR_OST1CLR, ost->base + OST_REG_OSTCR);
224 writel(OSTESR_OST1ENS, ost->base + OST_REG_OSTESR);
225 writel(~OSTMR_FMASK, ost->base + OST_REG_OSTMR);
226
227 return 0;
228 }
229
230 static irqreturn_t ingenic_ost_cevt_cb(int irq, void *dev_id)
231 {
232 struct clock_event_device *evt = dev_id;
233 struct ingenic_ost *ost = to_ingenic_ost(evt);
234
235 writel(OSTECR_OST1ENC, ost->base + OST_REG_OSTECR);
236
237 if (evt->event_handler)
238 evt->event_handler(evt);
239
240 return IRQ_HANDLED;
241 }
242
243 static int __init ingenic_ost_register_clock(struct ingenic_ost *ost,
244 unsigned int idx, const struct ingenic_ost_clk_info *info,
245 struct clk_hw_onecell_data *clocks)
246 {
247 struct ingenic_ost_clk *ost_clk;
248 int val, err;
249
250 ost_clk = kzalloc(sizeof(*ost_clk), GFP_KERNEL);
251 if (!ost_clk)
252 return -ENOMEM;
253
254 ost_clk->hw.init = &info->init_data;
255 ost_clk->idx = idx;
256 ost_clk->info = info;
257 ost_clk->ost = ost;
258
259 /* Reset clock divider */
260 val = readl(ost->base + info->ostccr_reg);
261 val &= ~(OSTCCR_PRESCALE1_MASK | OSTCCR_PRESCALE2_MASK);
262 writel(val, ost->base + info->ostccr_reg);
263
264 err = clk_hw_register(NULL, &ost_clk->hw);
265 if (err) {
266 kfree(ost_clk);
267 return err;
268 }
269
270 clocks->hws[idx] = &ost_clk->hw;
271
272 return 0;
273 }
274
275 static struct clk * __init ingenic_ost_get_clock(struct device_node *np, int id)
276 {
277 struct of_phandle_args args;
278
279 args.np = np;
280 args.args_count = 1;
281 args.args[0] = id;
282
283 return of_clk_get_from_provider(&args);
284 }
285
286 static int __init ingenic_ost_percpu_timer_init(struct device_node *np,
287 struct ingenic_ost *ost)
288 {
289 unsigned int timer_virq, channel = ost->percpu_timer_channel;
290 unsigned long rate;
291 int err;
292
293 ost->percpu_timer_clk = ingenic_ost_get_clock(np, channel);
294 if (IS_ERR(ost->percpu_timer_clk))
295 return PTR_ERR(ost->percpu_timer_clk);
296
297 err = clk_prepare_enable(ost->percpu_timer_clk);
298 if (err)
299 goto err_clk_put;
300
301 rate = clk_get_rate(ost->percpu_timer_clk);
302 if (!rate) {
303 err = -EINVAL;
304 goto err_clk_disable;
305 }
306
307 timer_virq = of_irq_get(np, 0);
308 if (!timer_virq) {
309 err = -EINVAL;
310 goto err_clk_disable;
311 }
312
313 snprintf(ost->name, sizeof(ost->name), "OST percpu timer");
314
315 err = request_irq(timer_virq, ingenic_ost_cevt_cb, IRQF_TIMER,
316 ost->name, &ost->cevt);
317 if (err)
318 goto err_irq_dispose_mapping;
319
320 ost->cevt.cpumask = cpumask_of(smp_processor_id());
321 ost->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
322 ost->cevt.name = ost->name;
323 ost->cevt.rating = 400;
324 ost->cevt.set_state_shutdown = ingenic_ost_cevt_set_state_shutdown;
325 ost->cevt.set_next_event = ingenic_ost_cevt_set_next;
326
327 clockevents_config_and_register(&ost->cevt, rate, 4, 0xffffffff);
328
329 return 0;
330
331 err_irq_dispose_mapping:
332 irq_dispose_mapping(timer_virq);
333 err_clk_disable:
334 clk_disable_unprepare(ost->percpu_timer_clk);
335 err_clk_put:
336 clk_put(ost->percpu_timer_clk);
337 return err;
338 }
339
340 static int __init ingenic_ost_global_timer_init(struct device_node *np,
341 struct ingenic_ost *ost)
342 {
343 unsigned int channel = ost->global_timer_channel;
344 struct clocksource *cs = &ost->cs;
345 unsigned long rate;
346 int err;
347
348 ost->global_timer_clk = ingenic_ost_get_clock(np, channel);
349 if (IS_ERR(ost->global_timer_clk))
350 return PTR_ERR(ost->global_timer_clk);
351
352 err = clk_prepare_enable(ost->global_timer_clk);
353 if (err)
354 goto err_clk_put;
355
356 rate = clk_get_rate(ost->global_timer_clk);
357 if (!rate) {
358 err = -EINVAL;
359 goto err_clk_disable;
360 }
361
362 /* Clear counter CNT registers */
363 writel(OSTCR_OST2CLR, ost->base + OST_REG_OSTCR);
364
365 /* Enable OST channel */
366 writel(OSTESR_OST2ENS, ost->base + OST_REG_OSTESR);
367
368 cs->name = "ingenic-ost";
369 cs->rating = 400;
370 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
371 cs->mask = CLOCKSOURCE_MASK(32);
372 cs->read = ingenic_ost_clocksource_read;
373
374 err = clocksource_register_hz(cs, rate);
375 if (err)
376 goto err_clk_disable;
377
378 return 0;
379
380 err_clk_disable:
381 clk_disable_unprepare(ost->global_timer_clk);
382 err_clk_put:
383 clk_put(ost->global_timer_clk);
384 return err;
385 }
386
387 static const struct ingenic_soc_info x1000_soc_info = {
388 .num_channels = 2,
389 };
390
391 static const struct of_device_id __maybe_unused ingenic_ost_of_match[] __initconst = {
392 { .compatible = "ingenic,x1000-ost", .data = &x1000_soc_info, },
393 { /* sentinel */ }
394 };
395
396 static int __init ingenic_ost_probe(struct device_node *np)
397 {
398 const struct of_device_id *id = of_match_node(ingenic_ost_of_match, np);
399 struct ingenic_ost *ost;
400 unsigned int i;
401 int ret;
402
403 ost = kzalloc(sizeof(*ost), GFP_KERNEL);
404 if (!ost)
405 return -ENOMEM;
406
407 ost->base = of_iomap(np, 0);
> 408 if (!ost->base) {
409 pr_err("%s: Failed to map OST registers\n", __func__);
410 goto err_free_ost;
411 }
412
413 ost->clk = of_clk_get_by_name(np, "ost");
414 if (IS_ERR(ost->clk)) {
415 ret = PTR_ERR(ost->clk);
416 pr_crit("%s: Cannot get OST clock\n", __func__);
417 goto err_free_ost;
418 }
419
420 ret = clk_prepare_enable(ost->clk);
421 if (ret) {
422 pr_crit("%s: Unable to enable OST clock\n", __func__);
423 goto err_put_clk;
424 }
425
426 ost->soc_info = id->data;
427
428 ost->clocks = kzalloc(struct_size(ost->clocks, hws, ost->soc_info->num_channels),
429 GFP_KERNEL);
430 if (!ost->clocks) {
431 ret = -ENOMEM;
432 goto err_clk_disable;
433 }
434
435 ost->clocks->num = ost->soc_info->num_channels;
436
437 for (i = 0; i < ost->clocks->num; i++) {
438 ret = ingenic_ost_register_clock(ost, i, &ingenic_ost_clk_info[i], ost->clocks);
439 if (ret) {
440 pr_crit("%s: Cannot register clock %d\n", __func__, i);
441 goto err_unregister_ost_clocks;
442 }
443 }
444
445 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ost->clocks);
446 if (ret) {
447 pr_crit("%s: Cannot add OF clock provider\n", __func__);
448 goto err_unregister_ost_clocks;
449 }
450
451 ost->percpu_timer_channel = OST_CLK_PERCPU_TIMER;
452 ost->global_timer_channel = OST_CLK_GLOBAL_TIMER;
453
454 ingenic_ost = ost;
455
456 return 0;
457
458 err_unregister_ost_clocks:
459 for (i = 0; i < ost->clocks->num; i++)
460 if (ost->clocks->hws[i])
461 clk_hw_unregister(ost->clocks->hws[i]);
462 kfree(ost->clocks);
463 err_clk_disable:
464 clk_disable_unprepare(ost->clk);
465 err_put_clk:
466 clk_put(ost->clk);
467 err_free_ost:
468 kfree(ost);
469 return ret;
470 }
471

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
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Next message: Michael Walle: "Re: [RFC] MFD's relationship with Device Tree (OF)"
Previous message: Qais Yousef: "Re: [PATCH v3 2/2] sched/uclamp: Protect uclamp fast path code with static key"
In reply to: kernel test robot: "Re: [PATCH 2/2] clocksource: Ingenic: Add support for the Ingenic X1000 OST."
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]