Re: [PATCH 4.19 023/206] PCI: aardvark: Dont blindly enable ASPM L0s and dont write to read-only register

[Pavel Machek]

Hi!

> > > [ Upstream commit 90c6cb4a355e7befcb557d217d1d8b8bd5875a05 ]
> > > 
> > > Trying to change Link Status register does not have any effect as this
> > > is a read-only register. Trying to overwrite bits for Negotiated Link
> > > Width does not make sense.
> > 
> > I don't quite get it. This says register is read only...
> > 
> > > In future proper change of link width can be done via Lane Count Select
> > > bits in PCIe Control 0 register.
> > > 
> > > Trying to unconditionally enable ASPM L0s via ASPM Control bits in Link
> > > Control register is wrong. There should be at least some detection if
> > > endpoint supports L0s as isn't mandatory.
> > 
> > ....and this says it is wrong to set the bits as ASPM L0 is not
> > mandatory.
> 
> Negotiated Link Width is in read-only 16bit Link Status register.
> 
> ASPM Control bits are in read-write 16bit Link Control register.
> 
> 
> That single write was via 32bit memory access which tried to overwrite
> both registers (Link Status and Link Control) at the same time.

Aha, thanks for explanation and sorry for the noise.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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