Re: [PATCH 1/2] clk: JZ4780: Add functions for enable and disable USB PHY.
From: Zhou Yanjie
Date: Sun Jun 28 2020 - 12:10:28 EST
Hi Paul,
å 2020/6/27 äå1:20, Paul Cercueil åé:
Hi Zhou,
Le sam. 27 juin 2020 Ã 0:48, åçæ (Zhou Yanjie)
<zhouyanjie@xxxxxxxxxxxxxx> a Ãcrit :
Add new functions to "jz4780_otg_phy_ops" to enable or disable the
USB PHY in the Ingenic JZ4780 SoC.
Tested-by: åæ (Zhou Zheng) <sernia.zhou@xxxxxxxxxxx>
Signed-off-by: åçæ (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>
---
Âdrivers/clk/ingenic/jz4780-cgu.c | 124
+++++++++++++++++++++++++--------------
Â1 file changed, 80 insertions(+), 44 deletions(-)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c
b/drivers/clk/ingenic/jz4780-cgu.c
index 6c5b8029cc8a..0ec50b9ab9c1 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -4,6 +4,7 @@
 *
 * Copyright (c) 2013-2015 Imagination Technologies
 * Author: Paul Burton <paul.burton@xxxxxxxx>
+ * Copyright (c) 2020 åçæ (Zhou Yanjie) <zhouyanjie@xxxxxxxxxxxxxx>
 */
Â#include <linux/clk-provider.h>
@@ -19,55 +20,57 @@
Â/* CGU register offsets */
Â#define CGU_REG_CLOCKCONTROLÂÂÂ 0x00
-#define CGU_REG_LCRÂÂÂÂÂÂÂÂÂÂÂ 0x04
-#define CGU_REG_APLLÂÂÂÂÂÂÂ 0x10
-#define CGU_REG_MPLLÂÂÂÂÂÂÂ 0x14
-#define CGU_REG_EPLLÂÂÂÂÂÂÂ 0x18
-#define CGU_REG_VPLLÂÂÂÂÂÂÂ 0x1c
-#define CGU_REG_CLKGR0ÂÂÂÂÂÂÂ 0x20
-#define CGU_REG_OPCRÂÂÂÂÂÂÂ 0x24
-#define CGU_REG_CLKGR1ÂÂÂÂÂÂÂ 0x28
-#define CGU_REG_DDRCDRÂÂÂÂÂÂÂ 0x2c
-#define CGU_REG_VPUCDRÂÂÂÂÂÂÂ 0x30
-#define CGU_REG_USBPCRÂÂÂÂÂÂÂ 0x3c
-#define CGU_REG_USBRDTÂÂÂÂÂÂÂ 0x40
-#define CGU_REG_USBVBFILÂÂÂ 0x44
-#define CGU_REG_USBPCR1ÂÂÂÂÂÂÂ 0x48
-#define CGU_REG_LP0CDRÂÂÂÂÂÂÂ 0x54
-#define CGU_REG_I2SCDRÂÂÂÂÂÂÂ 0x60
-#define CGU_REG_LP1CDRÂÂÂÂÂÂÂ 0x64
-#define CGU_REG_MSC0CDRÂÂÂÂÂÂÂ 0x68
-#define CGU_REG_UHCCDRÂÂÂÂÂÂÂ 0x6c
-#define CGU_REG_SSICDRÂÂÂÂÂÂÂ 0x74
-#define CGU_REG_CIMCDRÂÂÂÂÂÂÂ 0x7c
-#define CGU_REG_PCMCDRÂÂÂÂÂÂÂ 0x84
-#define CGU_REG_GPUCDRÂÂÂÂÂÂÂ 0x88
-#define CGU_REG_HDMICDRÂÂÂÂÂÂÂ 0x8c
-#define CGU_REG_MSC1CDRÂÂÂÂÂÂÂ 0xa4
-#define CGU_REG_MSC2CDRÂÂÂÂÂÂÂ 0xa8
-#define CGU_REG_BCHCDRÂÂÂÂÂÂÂ 0xac
-#define CGU_REG_CLOCKSTATUSÂÂÂ 0xd4
+#define CGU_REG_LCRÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 0x04
+#define CGU_REG_APLLÂÂÂÂÂÂÂÂÂÂÂ 0x10
+#define CGU_REG_MPLLÂÂÂÂÂÂÂÂÂÂÂ 0x14
+#define CGU_REG_EPLLÂÂÂÂÂÂÂÂÂÂÂ 0x18
+#define CGU_REG_VPLLÂÂÂÂÂÂÂÂÂÂÂ 0x1c
+#define CGU_REG_CLKGR0ÂÂÂÂÂÂÂÂÂÂÂ 0x20
+#define CGU_REG_OPCRÂÂÂÂÂÂÂÂÂÂÂ 0x24
+#define CGU_REG_CLKGR1ÂÂÂÂÂÂÂÂÂÂÂ 0x28
+#define CGU_REG_DDRCDRÂÂÂÂÂÂÂÂÂÂÂ 0x2c
+#define CGU_REG_VPUCDRÂÂÂÂÂÂÂÂÂÂÂ 0x30
+#define CGU_REG_USBPCRÂÂÂÂÂÂÂÂÂÂÂ 0x3c
+#define CGU_REG_USBRDTÂÂÂÂÂÂÂÂÂÂÂ 0x40
+#define CGU_REG_USBVBFILÂÂÂÂÂÂÂ 0x44
+#define CGU_REG_USBPCR1ÂÂÂÂÂÂÂÂÂÂÂ 0x48
+#define CGU_REG_LP0CDRÂÂÂÂÂÂÂÂÂÂÂ 0x54
+#define CGU_REG_I2SCDRÂÂÂÂÂÂÂÂÂÂÂ 0x60
+#define CGU_REG_LP1CDRÂÂÂÂÂÂÂÂÂÂÂ 0x64
+#define CGU_REG_MSC0CDRÂÂÂÂÂÂÂÂÂÂÂ 0x68
+#define CGU_REG_UHCCDRÂÂÂÂÂÂÂÂÂÂÂ 0x6c
+#define CGU_REG_SSICDRÂÂÂÂÂÂÂÂÂÂÂ 0x74
+#define CGU_REG_CIMCDRÂÂÂÂÂÂÂÂÂÂÂ 0x7c
+#define CGU_REG_PCMCDRÂÂÂÂÂÂÂÂÂÂÂ 0x84
+#define CGU_REG_GPUCDRÂÂÂÂÂÂÂÂÂÂÂ 0x88
+#define CGU_REG_HDMICDRÂÂÂÂÂÂÂÂÂÂÂ 0x8c
+#define CGU_REG_MSC1CDRÂÂÂÂÂÂÂÂÂÂÂ 0xa4
+#define CGU_REG_MSC2CDRÂÂÂÂÂÂÂÂÂÂÂ 0xa8
+#define CGU_REG_BCHCDRÂÂÂÂÂÂÂÂÂÂÂ 0xac
+#define CGU_REG_CLOCKSTATUSÂÂÂÂÂÂÂ 0xd4
If you want to reformat the code (add one level of indentation before
the values) then please do it in a following patch, otherwise it's
really hard to see what really changed.
Sure.
The rest looks good so far.
Cheers,
-Paul
Â/* bits within the OPCR register */
-#define OPCR_SPENDN0ÂÂÂÂÂÂÂ BIT(7)
-#define OPCR_SPENDN1ÂÂÂÂÂÂÂ BIT(6)
+#define OPCR_SPENDN0ÂÂÂÂÂÂÂÂÂÂÂ BIT(7)
+#define OPCR_SPENDN1ÂÂÂÂÂÂÂÂÂÂÂ BIT(6)
Â/* bits within the USBPCR register */
-#define USBPCR_USB_MODEÂÂÂÂÂÂÂ BIT(31)
+#define USBPCR_USB_MODEÂÂÂÂÂÂÂÂÂÂÂ BIT(31)
Â#define USBPCR_IDPULLUP_MASKÂÂÂ (0x3 << 28)
-#define USBPCR_COMMONONNÂÂÂ BIT(25)
-#define USBPCR_VBUSVLDEXTÂÂÂ BIT(24)
+#define USBPCR_COMMONONNÂÂÂÂÂÂÂ BIT(25)
+#define USBPCR_VBUSVLDEXTÂÂÂÂÂÂÂ BIT(24)
Â#define USBPCR_VBUSVLDEXTSELÂÂÂ BIT(23)
-#define USBPCR_PORÂÂÂÂÂÂÂ BIT(22)
-#define USBPCR_OTG_DISABLEÂÂÂ BIT(20)
+#define USBPCR_PORÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(22)
+#define USBPCR_SIDDQÂÂÂÂÂÂÂÂÂÂÂ BIT(21)
+#define USBPCR_OTG_DISABLEÂÂÂÂÂÂÂ BIT(20)
Â#define USBPCR_COMPDISTUNE_MASKÂÂÂ (0x7 << 17)
-#define USBPCR_OTGTUNE_MASKÂÂÂ (0x7 << 14)
+#define USBPCR_OTGTUNE_MASKÂÂÂÂÂÂÂ (0x7 << 14)
Â#define USBPCR_SQRXTUNE_MASKÂÂÂ (0x7 << 11)
Â#define USBPCR_TXFSLSTUNE_MASKÂÂÂ (0xf << 7)
Â#define USBPCR_TXPREEMPHTUNEÂÂÂ BIT(6)
Â#define USBPCR_TXHSXVTUNE_MASKÂÂÂ (0x3 << 4)
Â#define USBPCR_TXVREFTUNE_MASKÂÂÂ 0xf
+
Â/* bits within the USBPCR1 register */
Â#define USBPCR1_REFCLKSEL_SHIFTÂÂÂ 26
Â#define USBPCR1_REFCLKSEL_MASKÂÂÂ (0x3 << USBPCR1_REFCLKSEL_SHIFT)
@@ -78,13 +81,13 @@
Â#define USBPCR1_REFCLKDIV_48ÂÂÂ (0x2 << USBPCR1_REFCLKDIV_SHIFT)
Â#define USBPCR1_REFCLKDIV_24ÂÂÂ (0x1 << USBPCR1_REFCLKDIV_SHIFT)
Â#define USBPCR1_REFCLKDIV_12ÂÂÂ (0x0 << USBPCR1_REFCLKDIV_SHIFT)
-#define USBPCR1_USB_SELÂÂÂÂÂÂÂ BIT(28)
-#define USBPCR1_WORD_IF0ÂÂÂ BIT(19)
-#define USBPCR1_WORD_IF1ÂÂÂ BIT(18)
+#define USBPCR1_USB_SELÂÂÂÂÂÂÂÂÂÂÂ BIT(28)
+#define USBPCR1_WORD_IF0ÂÂÂÂÂÂÂ BIT(19)
+#define USBPCR1_WORD_IF1ÂÂÂÂÂÂÂ BIT(18)
Â/* bits within the USBRDT register */
-#define USBRDT_VBFIL_LD_ENÂÂÂ BIT(25)
-#define USBRDT_USBRDT_MASKÂÂÂ 0x7fffff
+#define USBRDT_VBFIL_LD_ENÂÂÂÂÂÂÂ BIT(25)
+#define USBRDT_USBRDT_MASKÂÂÂÂÂÂÂ 0x7fffff
Â/* bits within the USBVBFIL register */
Â#define USBVBFIL_IDDIGFIL_SHIFTÂÂÂ 16
@@ -92,11 +95,11 @@
Â#define USBVBFIL_USBVBFIL_MASKÂÂÂ (0xffff)
Â/* bits within the LCR register */
-#define LCR_PD_SCPUÂÂÂÂÂÂÂÂÂÂÂ BIT(31)
-#define LCR_SCPUSÂÂÂÂÂÂÂÂÂÂÂ BIT(27)
+#define LCR_PD_SCPUÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(31)
+#define LCR_SCPUSÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ BIT(27)
Â/* bits within the CLKGR1 register */
-#define CLKGR1_CORE1ÂÂÂÂÂÂÂ BIT(15)
+#define CLKGR1_CORE1ÂÂÂÂÂÂÂÂÂÂÂ BIT(15)
Âstatic struct ingenic_cgu *cgu;
@@ -206,6 +209,35 @@ static int jz4780_otg_phy_set_rate(struct clk_hw
*hw, unsigned long req_rate,
ÂÂÂÂ return 0;
Â}
+static int jz4780_otg_phy_enable(struct clk_hw *hw)
+{
+ÂÂÂ void __iomem *reg_opcrÂÂÂÂÂÂÂ = cgu->base + CGU_REG_OPCR;
+ÂÂÂ void __iomem *reg_usbpcrÂÂÂ = cgu->base + CGU_REG_USBPCR;
+
+ÂÂÂ writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
+ÂÂÂ writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ,
reg_usbpcr);
+ÂÂÂ return 0;
+}
+
+static void jz4780_otg_phy_disable(struct clk_hw *hw)
+{
+ÂÂÂ void __iomem *reg_opcrÂÂÂÂÂÂÂ = cgu->base + CGU_REG_OPCR;
+ÂÂÂ void __iomem *reg_usbpcrÂÂÂ = cgu->base + CGU_REG_USBPCR;
+
+ÂÂÂ writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
+ÂÂÂ writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ,
reg_usbpcr);
+}
+
+static int jz4780_otg_phy_is_enabled(struct clk_hw *hw)
+{
+ÂÂÂ void __iomem *reg_opcrÂÂÂÂÂÂÂ = cgu->base + CGU_REG_OPCR;
+ÂÂÂ void __iomem *reg_usbpcrÂÂÂ = cgu->base + CGU_REG_USBPCR;
+
+ÂÂÂ return (readl(reg_opcr) & OPCR_SPENDN0) &&
+ÂÂÂÂÂÂÂ !(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
+ÂÂÂÂÂÂÂ !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
+}
+
Âstatic const struct clk_ops jz4780_otg_phy_ops = {
ÂÂÂÂ .get_parent = jz4780_otg_phy_get_parent,
ÂÂÂÂ .set_parent = jz4780_otg_phy_set_parent,
@@ -213,6 +245,10 @@ static const struct clk_ops jz4780_otg_phy_ops = {
ÂÂÂÂ .recalc_rate = jz4780_otg_phy_recalc_rate,
ÂÂÂÂ .round_rate = jz4780_otg_phy_round_rate,
ÂÂÂÂ .set_rate = jz4780_otg_phy_set_rate,
+
+ÂÂÂ .enableÂÂÂÂÂÂÂ = jz4780_otg_phy_enable,
+ÂÂÂ .disableÂÂÂ = jz4780_otg_phy_disable,
+ÂÂÂ .is_enabledÂÂÂ = jz4780_otg_phy_is_enabled,
Â};
Âstatic int jz4780_core1_enable(struct clk_hw *hw)
--
2.11.0