[PATCH 4/5] dt-bindings: clk: versaclock5: add output drive mode property

[Luca Ceresoli]

Add a node with properties for each output port, and a property inside it
to describe the output drive mode.

Signed-off-by: Luca Ceresoli <luca@xxxxxxxxxxxxxxxx>
---
 .../bindings/clock/idt,versaclock5.yaml       | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
index d8b8e35f16d2..f0ee612f573b 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
@@ -50,6 +50,35 @@ properties:
   '#clock-cells':
     const: 1
 
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^out@[1-4]$":
+    type: object
+    description:
+      Description of one of the outputs (OUT1..OUT4).
+    properties:
+      idt,drive-mode:
+        description:
+          The output drive mode. See "Clock1 Output Configuration" in the
+          Versaclock 5/6/6E Family Register Description and Programming
+          Guide.
+          Allowed values are:-
+            * 0 = LVPECL
+            * 1 = CMOS
+            * 2 = HCSL33
+            * 3 = LVDS
+            * 4 = CMOS2
+            * 5 = CMOSD
+            * 6 = HCSL25
+        $ref: /schemas/types.yaml#/definitions/uint32
+        minimum: 0
+        maximum: 6
+
 required:
   - compatible
   - reg
@@ -107,6 +136,19 @@ examples:
             /* Connect XIN input to 25MHz reference */
             clocks = <&ref25m>;
             clock-names = "xin";
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            out@1 {
+                reg = <1>; /* OUT1 */
+                idt,drive-mode = <5>; /* CMOSD */
+            };
+
+            out@4 {
+                reg = <4>; /* OUT4 */
+                idt,drive-mode = <3>; /* LVDS */
+            };
         };
     };
 
-- 
2.27.0