Re: [PATCH] SPI LPC information kernel module

[Arnd Bergmann]

On Fri, Jul 3, 2020 at 10:43 PM Daniel Gutson <daniel@xxxxxxxxxxxxx> wrote:
> On Tue, Jun 30, 2020 at 5:58 PM Arnd Bergmann <arnd@xxxxxxxx> wrote:
>
> After analyzing the intel-spi driver, I came up to these observations that led
> me conclude that it is not what I need to use:
>
> * Some SPI Controllers have 0xFFFF as their VID DID bytes in the PCI
> config space. This causes that the PCI devices enumeration doesn't include them,
> and thus a PCI device driver won't be probed even despite listing the DID
> that the datasheet specifies. I effectively confirmed this by doing a PCI device
> driver and trying the intel-spi in systems with this characteristic. In short, the
> intel-spi driver doesn't work with these systems.

I don't understand what you mean here. How do *you* find the device if the
device-id is 0xffff?

My impression was that the spi-nor host is not a PCI device at all
but instead is a function on the mfd device, and probed as a
platform_driver with the "intel-spi" name.

> * Additionally, there is a difference of functionality: the intel-spi driver is a MTD,
> and -despite it effectively contains some of the DIDs my proposed driver
> supports- it doesn't offer an API to read the BIOS related registers (which is not the
> function read_register, since it reads chip registers). In fact, note that it reads
> HSFS from the PCI config space using MMIO, by just reading the mapped
> memory offset. The read register callback reads a different type of registers
> with a different mechanism (eg it does a writel before a readl). By being a MTD,
> it doesn't need to read for example the Bios Control register (which I need), or
> other registers that I need but are irrelevant for MTD operations.
>
> I should add a new interface to the driver just to read these registers or an
> interface to read an arbitrary offset from the mapped memory.
> * Finally, some of the registers I need are present in the PCI Config Space

Config space of *which* device in particular? Is this the Atom MFD device,
the SPI-NOR host, or something else?

> (others are in other places), but the offsets (and/or the offsets of the fields)
> vary depending on the architecture of the CPU or the PCH. That's why I
> first detect the architecture based on the VID/DID and then use the appropriate
> definition. Moreover, there are cases where the same registers  is obtained
> by reading the PCI CFG in some architectures, whereas it is obtained by
> reading MMIO in other architectures (eg Atom). All this information is provided
> in the Intel's datasheets.

Is this MMIO space part of a PCI device BAR, or how do you find it?
If it belongs to a PCI device, which one is this, and why can't there
be a driver for it?

> Because of these reasons, I'm proposing a misc (not-device) driver that supports
> many Intel architectures (and families) to expose the information.
> I understand your proposal to first enhance existing _device_ drivers, but I
> couldn't find suitable options.

Maybe try adding an interface to one of the drivers at first, and then extend
it to the other hardware after an initial code review. Do not bypass the driver
model or try to do everything at once with a single module that knows
details of multiple unrelated hardware implementations.

     Arnd