[PATCH] dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle

[Enric Balletbo i Serra]

The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU
general register files to know the DRAM type, so add a phandle to the
syscon that manages these registers.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx>
Reviewed-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: GaÃl PORTAY <gael.portay@xxxxxxxxxxxxx>
Acked-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx>
---
Following the discussion in [1] and after having [2] accepted, this
patch is a RESEND of a patch [3] that has already all the acks but for
some reason and my bad, I lost the tracking, didn't land. The patch adds
documentation for an already property implemented in the driver, so
resend the patch again. There is a slighty modification, the rockchip,pmu
property has been moved to be optional as is not really required.

Thanks,
  Enric

[1] https://lkml.org/lkml/2020/6/22/692
[2] https://lkml.org/lkml/2020/6/30/367
[3] https://patchwork.kernel.org/patch/10901593/

 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
index 0ec68141f85a..a10d1f6d85c6 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -18,6 +18,8 @@ Optional properties:
 			 format depends on the interrupt controller.
 			 It should be a DCF interrupt. When DDR DVFS finishes
 			 a DCF interrupt is triggered.
+- rockchip,pmu:		 Phandle to the syscon managing the "PMU general register
+			 files".
 
 Following properties relate to DDR timing:
 
-- 
2.27.0