Re: [PATCH v7 2/2] display/drm/bridge: TC358775 DSI/LVDS driver

From: Andrzej Hajda
Date: Fri Jul 10 2020 - 02:04:09 EST

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On 07.07.2020 10:25, Vinay Simha B N wrote:
> Andrzej,
>
> Please suggest.
>
> In general it should be in the reverse-order RESX then STBY, But
> As per the spec Datasheet Power off sequence is this Page 149, Section
> Power Supply On and Off Sequence
>
> regulators
> STBY
> RESX
>
> https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwiBmeWb2brqAhXO7HMBHZgaCTUQFjACegQIBxAB&url=https%3A%2F%2Fdownload.t-firefly.com%2Fproduct%2FRK3399%2FDocs%2FChip%2520Specifications%2FTC358774XBG_75XBG_V1%25204nm.pdf&usg=AOvVaw2kBuPv8FaZBNynGWCQHEfc
> <https://protect2.fireeye.com/v1/url?k=fc81046b-a14dcfaf-fc808f24-0cc47a314e9a-260fe757996adc0f&q=1&e=c54ac15e-86b9-4dd9-b17e-762132071a25&u=https%3A%2F%2Fwww.google.com%2Furl%3Fsa%3Dt%26rct%3Dj%26q%3D%26esrc%3Ds%26source%3Dweb%26cd%3D%26ved%3D2ahUKEwiBmeWb2brqAhXO7HMBHZgaCTUQFjACegQIBxAB%26url%3Dhttps%253A%252F%252Fdownload.t-firefly.com%252Fproduct%252FRK3399%252FDocs%252FChip%252520Specifications%252FTC358774XBG_75XBG_V1%2525204nm.pdf%26usg%3DAOvVaw2kBuPv8FaZBNynGWCQHEfc>
>

I guess you misread the diagram, it should be read from left to
right(not top-bottom), and you have power off sequence:

RESX

STDBY

VDDC

VDD_LVDS

VDDIO

> Regarding data-lanes
> -data-lanes value does appear later from the mdp->dsi0 tree
> -We need to pick dynamically data-lanes of the dsi set, based on this
> we need to set in the bridge.
> Otherwise we are already setting in dsi0 ports as <0 1 2 3> , again we
> need to set it in the bridge tree.
> - There is no helper function to get the data-lanes of the DSI

The code asks for proper helper, but since there is no such I think it
can stay as is.

Regards

Andrzej

>
> On Tue, Jul 7, 2020 at 12:15 PM Andrzej Hajda <a.hajda@xxxxxxxxxxx
> <mailto:a.hajda@xxxxxxxxxxx>> wrote:
>
>
> On 04.07.2020 11:24, Vinay Simha BN wrote:
> > This driver is tested with two panels individually with
> Apq8016-IFC6309 board
> >
> https://protect2.fireeye.com/url?k=fe87a8ec-a3e0ecca-fe8623a3-0cc47a31384a-ffbc547df1141490&q=1&u=https%3A%2F%2Fwww.inforcecomputing.com%2Fproducts%2Fsingle-board-computers-sbc%2Fqualcomm-snapdragon-410-inforce-6309-micro-sbc
> >
> > 1. 1366x768@60 auo,b101xtn01 data-mapping = "jeida-24"
> > 2. 800x480@60 innolux,at070tn92 data-mapping = "vesa-24"
> >
> > - added SPDX identifier license
> > - updated alphabetic order of headers
> > - replaced u32 instead of uint32_t
> > - magic number to macros for CLRSI and mux registers
> > - mdelay to usleep_range
> > - added bus_formats
> > - removed drm_connector_status
> > - regulator enable and disable with proper orders and delays
> >Â Â as per the spec
> > - devm_drm_panel_bridge_add method used instead of panel
> >Â Â description modified
> > - dual port implemented
> > - panel->connector_type removed
> > - ~vsdelay dynamic value set based on the
> >Â Â calculation of dsi speed, output speed, blanking
> > - help modified
> > - display_timings naming local variables
> > - check for bus_formats unsupported
> > - error handling enpoint data-lanes
> > - Kconfig proper indentation
> > - GENMASK and FIELD_PREP used
> > - bus_formats handeld in mode_valid
> > - MODE_CLOCK_HIGH handled properly
> > - len initialized
> > - static function for mode_valid
> >
> > Signed-off-by: Vinay Simha BN <simhavcs@xxxxxxxxx
> <mailto:simhavcs@xxxxxxxxx>>
> > ---
> > v1:
> >Â ÂInitial version
> >
> > v2:
> > * Andrzej Hajda review comments incorporated
> >Â Â SPDX identifier
> >Â Â development debug removed
> >Â Â alphabetic order headers
> >Â Â u32 instead of unit32_t
> >Â Â magic numbers to macros for CLRSI and mux registers
> >Â Â ignored return value
> >
> > * Laurent Pinchart review comments incorporated
> >Â Â mdelay to usleep_range
> >Â Â bus_formats added
> >
> > v3:
> > * Andrzej Hajda review comments incorporated
> >Â Â drm_connector_status removed
> >Â Â u32 rev removed and local variabl is used
> >Â Â regulator enable disable with proper orders and delays
> >Â Â as per the spec
> >Â Â devm_drm_panel_bridge_add method used instead of panel
> >Â Â description modified
> >Â Â dual port implemented
> >
> > v4:
> > * Sam Ravnborg review comments incorporated
> >Â Â panel->connector_type removed
> >
> > * Reported-by: kernel test robot <lkp@xxxxxxxxx
> <mailto:lkp@xxxxxxxxx>>
> >Â Â parse_dt to static function
> >Â Â removed the if (endpoint), since data-lanes has to be
> >Â Â present for dsi dts ports
> >
> > v5:
> >Â Â ~vsdelay dynamic value set based on the
> >Â Â calculation of dsi speed, output speed, blanking
> >
> > v6:
> > * Sam Ravnborg review comments incorporated
> >Â Â help modified
> >Â Â display_timings naming local variables
> >Â Â check for bus_formats unsupported
> >Â Â error handling enpoint data-lanes
> >
> > v7:
> > * Sam Ravnborg review comments incorporated
> >Â Â Kconfig proper indentation
> >Â Â GENMASK and FIELD_PREP used
> >Â Â bus_formats handeld in mode_valid
> >Â Â MODE_CLOCK_HIGH handled properly
> >
> > * Reported-by: kernel test robot <lkp@xxxxxxxxx
> <mailto:lkp@xxxxxxxxx>>
> >Â Â len initialized
> >Â Â static function for mode_valid
> > ---
> >Â Âdrivers/gpu/drm/bridge/KconfigÂ Â |Â 10 +
> >Â Âdrivers/gpu/drm/bridge/MakefileÂ Â|Â Â1 +
> >Â Âdrivers/gpu/drm/bridge/tc358775.c | 757
> ++++++++++++++++++++++++++++++
> >Â Â3 files changed, 768 insertions(+)
> >Â Âcreate mode 100644 drivers/gpu/drm/bridge/tc358775.c
> >
> > diff --git a/drivers/gpu/drm/bridge/Kconfig
> b/drivers/gpu/drm/bridge/Kconfig
> > index 43271c21d3fc..25c3097c4003 100644
> > --- a/drivers/gpu/drm/bridge/Kconfig
> > +++ b/drivers/gpu/drm/bridge/Kconfig
> > @@ -181,6 +181,16 @@ config DRM_TOSHIBA_TC358768
> >Â Â Â Âhelp
> >Â Â Â Â ÂToshiba TC358768AXBG/TC358778XBG DSI bridge chip driver.
> >
> > +config DRM_TOSHIBA_TC358775
> > +Â Â Âtristate "Toshiba TC358775 DSI/LVDS bridge"
> > +Â Â Âdepends on OF
> > +Â Â Âselect DRM_KMS_HELPER
> > +Â Â Âselect REGMAP_I2C
> > +Â Â Âselect DRM_PANEL
> > +Â Â Âselect DRM_MIPI_DSI
> > +Â Â Âhelp
> > +Â Â Â ÂToshiba TC358775 DSI/LVDS bridge chip driver.
> > +
> >Â Âconfig DRM_TI_TFP410
> >Â Â Â Âtristate "TI TFP410 DVI/HDMI bridge"
> >Â Â Â Âdepends on OF
> > diff --git a/drivers/gpu/drm/bridge/Makefile
> b/drivers/gpu/drm/bridge/Makefile
> > index d63d4b7e4347..23c770b3bfe4 100644
> > --- a/drivers/gpu/drm/bridge/Makefile
> > +++ b/drivers/gpu/drm/bridge/Makefile
> > @@ -15,6 +15,7 @@ obj-$(CONFIG_DRM_THINE_THC63LVD1024) +=
> thc63lvd1024.o
> >Â Âobj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o
> >Â Âobj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
> >Â Âobj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
> > +obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
> >Â Âobj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
> >Â Âobj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
> >Â Âobj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
> > diff --git a/drivers/gpu/drm/bridge/tc358775.c
> b/drivers/gpu/drm/bridge/tc358775.c
> > new file mode 100644
> > index 000000000000..6494179369a6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/tc358775.c
> > @@ -0,0 +1,757 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * tc358775 DSI to LVDS bridge driver
> > + *
> > + * Copyright (C) 2020 SMART Wireless Computing
> > + * Author: Vinay Simha BN <simhavcs@xxxxxxxxx
> <mailto:simhavcs@xxxxxxxxx>>
> > + *
> > + */
> > +/* #define DEBUG */
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/device.h>
> > +#include <linux/gpio/consumer.h>
> > +#include <linux/i2c.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/regulator/consumer.h>
> > +#include <linux/slab.h>
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_bridge.h>
> > +#include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_dp_helper.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_panel.h>
> > +#include <drm/drm_probe_helper.h>
> > +
> > +#define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start,
> end), val)
> > +
> > +/* Registers */
> > +
> > +/* DSI D-PHY Layer Registers */
> > +#define D0W_DPHYCONTTXÂ 0x0004Â /* Data Lane 0 DPHY Tx Control */
> > +#define CLW_DPHYCONTRXÂ 0x0020Â /* Clock Lane DPHY Rx Control */
> > +#define D0W_DPHYCONTRXÂ 0x0024Â /* Data Lane 0 DPHY Rx Control */
> > +#define D1W_DPHYCONTRXÂ 0x0028Â /* Data Lane 1 DPHY Rx Control */
> > +#define D2W_DPHYCONTRXÂ 0x002CÂ /* Data Lane 2 DPHY Rx Control */
> > +#define D3W_DPHYCONTRXÂ 0x0030Â /* Data Lane 3 DPHY Rx Control */
> > +#define COM_DPHYCONTRXÂ 0x0038Â /* DPHY Rx Common Control */
> > +#define CLW_CNTRLÂ Â Â Â0x0040Â /* Clock Lane Control */
> > +#define D0W_CNTRLÂ Â Â Â0x0044Â /* Data Lane 0 Control */
> > +#define D1W_CNTRLÂ Â Â Â0x0048Â /* Data Lane 1 Control */
> > +#define D2W_CNTRLÂ Â Â Â0x004CÂ /* Data Lane 2 Control */
> > +#define D3W_CNTRLÂ Â Â Â0x0050Â /* Data Lane 3 Control */
> > +#define DFTMODE_CNTRLÂ Â0x0054Â /* DFT Mode Control */
> > +
> > +/* DSI PPI Layer Registers */
> > +#define PPI_STARTPPIÂ Â 0x0104Â /* START control bit of PPI-TX
> function. */
> > +#define PPI_START_FUNCTIONÂ Â Â 1
> > +
> > +#define PPI_BUSYPPIÂ Â Â0x0108
> > +#define PPI_LINEINITCNT 0x0110Â /* Line Initialization Wait
> CounterÂ */
> > +#define PPI_LPTXTIMECNT 0x0114
> > +#define PPI_LANEENABLEÂ 0x0134Â /* Enables each lane at the PPI
> layer. */
> > +#define PPI_TX_RX_TAÂ Â 0x013CÂ /* DSI Bus Turn Around timing
> parameters */
> > +
> > +/* Analog timer function enable */
> > +#define PPI_CLS_ATMRÂ Â 0x0140Â /* Delay for Clock Lane in LPRXÂ */
> > +#define PPI_D0S_ATMRÂ Â 0x0144Â /* Delay for Data Lane 0 in LPRX */
> > +#define PPI_D1S_ATMRÂ Â 0x0148Â /* Delay for Data Lane 1 in LPRX */
> > +#define PPI_D2S_ATMRÂ Â 0x014CÂ /* Delay for Data Lane 2 in LPRX */
> > +#define PPI_D3S_ATMRÂ Â 0x0150Â /* Delay for Data Lane 3 in LPRX */
> > +
> > +#define PPI_D0S_CLRSIPOCOUNTÂ Â 0x0164Â /* For lane 0 */
> > +#define PPI_D1S_CLRSIPOCOUNTÂ Â 0x0168Â /* For lane 1 */
> > +#define PPI_D2S_CLRSIPOCOUNTÂ Â 0x016CÂ /* For lane 2 */
> > +#define PPI_D3S_CLRSIPOCOUNTÂ Â 0x0170Â /* For lane 3 */
> > +
> > +#define CLS_PREÂ Â Â Â Â0x0180Â /* Digital Counter inside of
> PHY IO */
> > +#define D0S_PREÂ Â Â Â Â0x0184Â /* Digital Counter inside of
> PHY IO */
> > +#define D1S_PREÂ Â Â Â Â0x0188Â /* Digital Counter inside of
> PHY IO */
> > +#define D2S_PREÂ Â Â Â Â0x018CÂ /* Digital Counter inside of
> PHY IO */
> > +#define D3S_PREÂ Â Â Â Â0x0190Â /* Digital Counter inside of
> PHY IO */
> > +#define CLS_PREPÂ Â Â Â 0x01A0Â /* Digital Counter inside of
> PHY IO */
> > +#define D0S_PREPÂ Â Â Â 0x01A4Â /* Digital Counter inside of
> PHY IO */
> > +#define D1S_PREPÂ Â Â Â 0x01A8Â /* Digital Counter inside of
> PHY IO */
> > +#define D2S_PREPÂ Â Â Â 0x01ACÂ /* Digital Counter inside of
> PHY IO */
> > +#define D3S_PREPÂ Â Â Â 0x01B0Â /* Digital Counter inside of
> PHY IO */
> > +#define CLS_ZEROÂ Â Â Â 0x01C0Â /* Digital Counter inside of
> PHY IO */
> > +#define D0S_ZEROÂ Â Â Â 0x01C4Â /* Digital Counter inside of
> PHY IO */
> > +#define D1S_ZEROÂ Â Â Â 0x01C8Â /* Digital Counter inside of
> PHY IO */
> > +#define D2S_ZEROÂ Â Â Â 0x01CCÂ /* Digital Counter inside of
> PHY IO */
> > +#define D3S_ZEROÂ Â Â Â 0x01D0Â /* Digital Counter inside of
> PHY IO */
> > +
> > +#define PPI_CLRFLGÂ Â Â 0x01E0Â /* PRE Counters has reached set
> values */
> > +#define PPI_CLRSIPOÂ Â Â0x01E4Â /* Clear SIPO values, Slave
> mode use only. */
> > +#define HSTIMEOUTÂ Â Â Â0x01F0Â /* HS Rx Time Out Counter */
> > +#define HSTIMEOUTENABLE 0x01F4Â /* Enable HS Rx Time Out Counter */
> > +#define DSI_STARTDSIÂ Â 0x0204Â /* START control bit of DSI-TX
> function */
> > +#define DSI_RX_START 1
> > +
> > +#define DSI_BUSYDSIÂ Â Â0x0208
> > +#define DSI_LANEENABLEÂ 0x0210Â /* Enables each lane at the
> Protocol layer. */
> > +#define DSI_LANESTATUS0 0x0214Â /* Displays lane is in HS RX
> mode. */
> > +#define DSI_LANESTATUS1 0x0218Â /* Displays lane is in ULPS or
> STOP state */
> > +
> > +#define DSI_INTSTATUSÂ Â0x0220Â /* Interrupt Status */
> > +#define DSI_INTMASKÂ Â Â0x0224Â /* Interrupt Mask */
> > +#define DSI_INTCLRÂ Â Â 0x0228Â /* Interrupt Clear */
> > +#define DSI_LPTXTOÂ Â Â 0x0230Â /* Low Power Tx Time Out Counter */
> > +
> > +#define DSIERRCNTÂ Â Â Â0x0300Â /* DSI Error Count */
> > +#define APLCTRLÂ Â Â Â Â0x0400Â /* Application Layer Control */
> > +#define RDPKTLNÂ Â Â Â Â0x0404Â /* Command Read Packet Length */
> > +
> > +#define VPCTRLÂ Â Â Â Â 0x0450Â /* Video Path Control */
> > +#define HTIM1Â Â Â Â Â Â0x0454Â /* Horizontal Timing Control 1 */
> > +#define HTIM2Â Â Â Â Â Â0x0458Â /* Horizontal Timing Control 2 */
> > +#define VTIM1Â Â Â Â Â Â0x045CÂ /* Vertical Timing Control 1 */
> > +#define VTIM2Â Â Â Â Â Â0x0460Â /* Vertical Timing Control 2 */
> > +#define VFUENÂ Â Â Â Â Â0x0464Â /* Video Frame Timing Update
> Enable */
> > +#define VFUEN_ENÂ Â ÂBIT(0)Â /* Upload Enable */
> > +
> > +/* Mux Input Select for LVDS LINK Input */
> > +#define LV_MX0003Â Â Â Â 0x0480Â /* Bit 0 to 3 */
> > +#define LV_MX0407Â Â Â Â 0x0484Â /* Bit 4 to 7 */
> > +#define LV_MX0811Â Â Â Â 0x0488Â /* Bit 8 to 11 */
> > +#define LV_MX1215Â Â Â Â 0x048CÂ /* Bit 12 to 15 */
> > +#define LV_MX1619Â Â Â Â 0x0490Â /* Bit 16 to 19 */
> > +#define LV_MX2023Â Â Â Â 0x0494Â /* Bit 20 to 23 */
> > +#define LV_MX2427Â Â Â Â 0x0498Â /* Bit 24 to 27 */
> > +#define LV_MX(b0, b1, b2, b3)Â Â Â Â (FLD_VAL(b0, 4, 0) |
> FLD_VAL(b1, 12, 8) | \
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â ÂFLD_VAL(b2, 20, 16) | FLD_VAL(b3,
> 28, 24))
> > +
> > +/* Input bit numbers used in mux registers */
> > +enum {
> > +Â Â ÂLVI_R0,
> > +Â Â ÂLVI_R1,
> > +Â Â ÂLVI_R2,
> > +Â Â ÂLVI_R3,
> > +Â Â ÂLVI_R4,
> > +Â Â ÂLVI_R5,
> > +Â Â ÂLVI_R6,
> > +Â Â ÂLVI_R7,
> > +Â Â ÂLVI_G0,
> > +Â Â ÂLVI_G1,
> > +Â Â ÂLVI_G2,
> > +Â Â ÂLVI_G3,
> > +Â Â ÂLVI_G4,
> > +Â Â ÂLVI_G5,
> > +Â Â ÂLVI_G6,
> > +Â Â ÂLVI_G7,
> > +Â Â ÂLVI_B0,
> > +Â Â ÂLVI_B1,
> > +Â Â ÂLVI_B2,
> > +Â Â ÂLVI_B3,
> > +Â Â ÂLVI_B4,
> > +Â Â ÂLVI_B5,
> > +Â Â ÂLVI_B6,
> > +Â Â ÂLVI_B7,
> > +Â Â ÂLVI_HS,
> > +Â Â ÂLVI_VS,
> > +Â Â ÂLVI_DE,
> > +Â Â ÂLVI_L0
> > +};
> > +
> > +#define LVCFGÂ Â Â Â Â Â0x049CÂ /* LVDS Configuration */
> > +#define LVPHY0Â Â Â Â Â 0x04A0Â /* LVDS PHY 0 */
> > +#define LV_PHY0_RST(v)Â Â Â Â Â FLD_VAL(v, 22, 22) /* PHY reset */
> > +#define LV_PHY0_IS(v)Â Â Â Â Â ÂFLD_VAL(v, 15, 14)
> > +#define LV_PHY0_ND(v)Â Â Â Â Â ÂFLD_VAL(v, 4, 0) /* Frequency
> range select */
> > +#define LV_PHY0_PRBS_ON(v)Â Â Â FLD_VAL(v, 20, 16) /*
> Clock/Data Flag pins */
> > +
> > +#define LVPHY1Â Â Â Â Â 0x04A4Â /* LVDS PHY 1 */
> > +#define SYSSTATÂ Â Â Â Â0x0500Â /* System StatusÂ */
> > +#define SYSRSTÂ Â Â Â Â 0x0504Â /* System ResetÂ */
> > +
> > +#define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
> > +#define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
> > +#define SYS_RST_LCDÂ BIT(2) /* Reset LCD controller */
> > +#define SYS_RST_BMÂ ÂBIT(3) /* Reset Bus Management controller */
> > +#define SYS_RST_DSIRXÂ Â Â Â BIT(4) /* Reset DSI-RX and App
> controller */
> > +#define SYS_RST_REGÂ BIT(5) /* Reset Register module */
> > +
> > +/* GPIO Registers */
> > +#define GPIOCÂ Â Â Â Â Â0x0520Â /* GPIO ControlÂ */
> > +#define GPIOOÂ Â Â Â Â Â0x0524Â /* GPIO OutputÂ */
> > +#define GPIOIÂ Â Â Â Â Â0x0528Â /* GPIO InputÂ */
> > +
> > +/* I2C Registers */
> > +#define I2CTIMCTRLÂ Â Â 0x0540Â /* I2C IF Timing and Enable
> Control */
> > +#define I2CMADDRÂ Â Â Â 0x0544Â /* I2C Master Addressing */
> > +#define WDATAQÂ Â Â Â Â 0x0548Â /* Write Data Queue */
> > +#define RDATAQÂ Â Â Â Â 0x054CÂ /* Read Data Queue */
> > +
> > +/* Chip ID and Revision ID Register */
> > +#define IDREGÂ Â Â Â Â Â0x0580
> > +
> > +#define LPX_PERIODÂ Â Â Â Â Â4
> > +#define TTA_GETÂ Â Â Â Â Â Â Â Â Â Â 0x40000
> > +#define TTA_SUREÂ Â Â Â Â Â Â6
> > +#define SINGLE_LINKÂ Â Â Â Â 1
> > +#define DUAL_LINKÂ Â Â Â Â Â 2
> > +
> > +#define TC358775XBG_IDÂ 0x00007500
> > +
> > +/* Debug Registers */
> > +#define DEBUG00Â Â Â Â Â0x05A0Â /* Debug */
> > +#define DEBUG01Â Â Â Â Â0x05A4Â /* LVDS Data */
> > +
> > +#define DSI_CLEN_BITÂ Â Â Â ÂBIT(0)
> > +#define DIVIDE_BY_3Â Â Â Â Â 3 /* PCLK=DCLK/3 */
> > +#define DIVIDE_BY_6Â Â Â Â Â 6 /* PCLK=DCLK/6 */
> > +#define LVCFG_LVEN_BITÂ Â Â Â Â Â Â ÂBIT(0)
> > +
> > +#define L0EN BIT(1)
> > +
> > +#define TC358775_VPCTRL_VSDELAY__MASKÂ Â Â Â 0x3FF00000
> > +#define TC358775_VPCTRL_VSDELAY__SHIFTÂ Â Â Â20
> > +static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
> > +{
> > +Â Â Âreturn ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
> > +Â Â Â Â Â Â Â Â Â Â ÂTC358775_VPCTRL_VSDELAY__MASK;
> > +}
> > +
> > +#define TC358775_VPCTRL_OPXLFMT__MASKÂ Â Â Â 0x00000100
> > +#define TC358775_VPCTRL_OPXLFMT__SHIFTÂ Â Â Â8
> > +static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
> > +{
> > +Â Â Âreturn ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
> > +Â Â Â Â Â Â Â Â Â Â ÂTC358775_VPCTRL_OPXLFMT__MASK;
> > +}
> > +
> > +#define TC358775_VPCTRL_MSF__MASKÂ Â 0x00000001
> > +#define TC358775_VPCTRL_MSF__SHIFTÂ Â0
> > +static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
> > +{
> > +Â Â Âreturn ((val) << TC358775_VPCTRL_MSF__SHIFT) &
> > +Â Â Â Â Â Â Â Â Â Â ÂTC358775_VPCTRL_MSF__MASK;
> > +}
> > +
> > +#define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0
> > +#define TC358775_LVCFG_PCLKDIV__SHIFTÂ Â Â Â 4
> > +static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
> > +{
> > +Â Â Âreturn ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
> > +Â Â Â Â Â Â Â Â Â Â ÂTC358775_LVCFG_PCLKDIV__MASK;
> > +}
> > +
> > +#define TC358775_LVCFG_LVDLINK__MASK Â Â Â0x00000002
> > +#define TC358775_LVCFG_LVDLINK__SHIFT Â Â 0
> > +static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
> > +{
> > +Â Â Âreturn ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
> > +Â Â Â Â Â Â Â Â Â Â ÂTC358775_LVCFG_LVDLINK__MASK;
> > +}
> > +
> > +enum tc358775_ports {
> > +Â Â ÂTC358775_DSI_IN,
> > +Â Â ÂTC358775_LVDS_OUT0,
> > +Â Â ÂTC358775_LVDS_OUT1,
> > +};
> > +
> > +struct tc_data {
> > +Â Â Âstruct i2c_clientÂ Â Â Â*i2c;
> > +Â Â Âstruct deviceÂ Â Â Â Â Â*dev;
> > +
> > +Â Â Âstruct drm_bridgeÂ Â Â Âbridge;
> > +Â Â Âstruct drm_bridgeÂ Â Â Â*panel_bridge;
> > +
> > +Â Â Âstruct device_node *host_node;
> > +Â Â Âstruct mipi_dsi_device *dsi;
> > +Â Â Âu8 num_dsi_lanes;
> > +
> > +Â Â Âstruct regulatorÂ Â Â Â *vdd;
> > +Â Â Âstruct regulatorÂ Â Â Â *vddio;
> > +Â Â Âstruct gpio_descÂ Â Â Â *reset_gpio;
> > +Â Â Âstruct gpio_descÂ Â Â Â *stby_gpio;
> > +Â Â Âu8Â Â Â Â Â Â Â Â Â Â Â lvds_link; /* single-link or
> dual-link */
> > +Â Â Âu8Â Â Â Â Â Â Â Â Â Â Â bpc;
> > +};
> > +
> > +static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
> > +{
> > +Â Â Âreturn container_of(b, struct tc_data, bridge);
> > +}
> > +
> > +static void tc_bridge_pre_enable(struct drm_bridge *bridge)
> > +{
> > +Â Â Âstruct tc_data *tc = bridge_to_tc(bridge);
> > +Â Â Âstruct device *dev = &tc->dsi->dev;
> > +Â Â Âint ret;
> > +
> > +Â Â Âret = regulator_enable(tc->vddio);
> > +Â Â Âif (ret < 0)
> > +Â Â Â Â Â Â Âdev_err(dev, "regulator vddio enable failed,
> %d\n", ret);
> > +Â Â Âusleep_range(10000, 11000);
> > +
> > +Â Â Âret = regulator_enable(tc->vdd);
> > +Â Â Âif (ret < 0)
> > +Â Â Â Â Â Â Âdev_err(dev, "regulator vdd enable failed, %d\n",
> ret);
> > +Â Â Âusleep_range(10000, 11000);
> > +
> > +Â Â Âgpiod_set_value(tc->stby_gpio, 0);
> > +Â Â Âusleep_range(10000, 11000);
> > +
> > +Â Â Âgpiod_set_value(tc->reset_gpio, 0);
> > +Â Â Âusleep_range(10, 20);
> > +}
> > +
> > +static void tc_bridge_post_disable(struct drm_bridge *bridge)
> > +{
> > +Â Â Âstruct tc_data *tc = bridge_to_tc(bridge);
> > +Â Â Âstruct device *dev = &tc->dsi->dev;
> > +Â Â Âint ret;
> > +
> > +Â Â Âret = regulator_disable(tc->vddio);
> > +Â Â Âif (ret < 0)
> > +Â Â Â Â Â Â Âdev_err(dev, "regulator vddio disable failed,
> %d\n", ret);
> > +Â Â Âusleep_range(10000, 11000);
> > +
> > +Â Â Âret = regulator_disable(tc->vdd);
> > +Â Â Âif (ret < 0)
> > +Â Â Â Â Â Â Âdev_err(dev, "regulator vdd disable failed, %d\n",
> ret);
> > +Â Â Âusleep_range(10000, 11000);
> > +
> > +Â Â Âgpiod_set_value(tc->stby_gpio, 1);
> > +Â Â Âusleep_range(10000, 11000);
> > +
> > +Â Â Âgpiod_set_value(tc->reset_gpio, 1);
> > +Â Â Âusleep_range(10, 20);
>
>
> Power off order is incorrect (I have already commented it at least
> once).
>
>
> > +}
> > +
> > +static u32 d2l_read(struct i2c_client *i2c, u16 reg)
> > +{
> > +Â Â Âint ret;
> > +Â Â Âu8 val[4];
> > +Â Â Âu8 addr[] = {(reg >> 8) & 0xff, reg & 0xff};
> > +Â Â Âu32 value;
> > +
> > +Â Â Âret = i2c_master_send(i2c, addr, sizeof(reg));
> > +Â Â Âif (ret < 0)
> > +Â Â Â Â Â Â Âgoto fail;
> > +
> > +Â Â Âret = i2c_master_recv(i2c, val, sizeof(value));
> > +Â Â Âif (ret < 0)
> > +Â Â Â Â Â Â Âgoto fail;
> > +
> > +Â Â Âvalue = val[3] << 24 | val[2] << 16 | val[1] << 8 | val[0];
>
>
> Please use le32_to_cpu or similar macro.
>
>
> > +
> > +Â Â Âpr_debug("d2l: I2C : reg:%04x value:%08x\n", reg, value);
> > +
> > +Â Â Âreturn value;
> > +
> > +fail:
> > +Â Â Âdev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
> > +Â Â Â Â Â Â Âret, reg);
> > +Â Â Âreturn 0;
> > +}
> > +
> > +static void d2l_write(struct i2c_client *i2c, u16 reg, u32 val)
> > +{
> > +Â Â Âu8 buf[6];
> > +Â Â Âint ret;
> > +
> > +Â Â Âbuf[0] = reg >> 8;
> > +Â Â Âbuf[1] = reg & 0xFF;
> > +Â Â Âbuf[2] = (val >> 0) & 0xFF;
> > +Â Â Âbuf[3] = (val >> 8) & 0xFF;
> > +Â Â Âbuf[4] = (val >> 16) & 0xFF;
> > +Â Â Âbuf[5] = (val >> 24) & 0xFF;
>
>
> put_unaligned_le16(reg, buf);
>
> put_unaligned_le32(reg, buf+2);
>
>
> > +
> > +Â Â Âret = i2c_master_send(i2c, buf, ARRAY_SIZE(buf));
> > +Â Â Âif (ret < 0)
> > +Â Â Â Â Â Â Âdev_err(&i2c->dev, "Error %d writing to subaddress
> 0x%x\n",
> > +Â Â Â Â Â Â Â Â Â Â Âret, reg);
> > +}
> > +
> > +/* helper function to access bus_formats */
> > +static struct drm_connector *get_connector(struct drm_encoder
> *encoder)
> > +{
> > +Â Â Âstruct drm_device *dev = encoder->dev;
> > +Â Â Âstruct drm_connector *connector;
> > +
> > +Â Â Âlist_for_each_entry(connector,
> &dev->mode_config.connector_list, head)
> > +Â Â Â Â Â Â Âif (connector->encoder == encoder)
> > +Â Â Â Â Â Â Â Â Â Â Âreturn connector;
> > +
> > +Â Â Âreturn NULL;
> > +}
> > +
> > +static void tc_bridge_enable(struct drm_bridge *bridge)
> > +{
> > +Â Â Âstruct tc_data *tc = bridge_to_tc(bridge);
> > +Â Â Âu32 hback_porch, hsync_len, hfront_porch, hactive, htime1,
> htime2;
> > +Â Â Âu32 vback_porch, vsync_len, vfront_porch, vactive, vtime1,
> vtime2;
> > +Â Â Âu32 val = 0;
> > +Â Â Âu16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
> > +Â Â Âstruct drm_display_mode *mode;
> > +Â Â Âstruct drm_connector *connector =
> get_connector(bridge->encoder);
> > +
> > +Â Â Âmode = &bridge->encoder->crtc->state->adjusted_mode;
> > +
> > +Â Â Âhback_porch = mode->htotal - mode->hsync_end;
> > +Â Â Âhsync_lenÂ = mode->hsync_end - mode->hsync_start;
> > +Â Â Âvback_porch = mode->vtotal - mode->vsync_end;
> > +Â Â Âvsync_lenÂ = mode->vsync_end - mode->vsync_start;
> > +
> > +Â Â Âhtime1 = (hback_porch << 16) + hsync_len;
> > +Â Â Âvtime1 = (vback_porch << 16) + vsync_len;
> > +
> > +Â Â Âhfront_porch = mode->hsync_start - mode->hdisplay;
> > +Â Â Âhactive = mode->hdisplay;
> > +Â Â Âvfront_porch = mode->vsync_start - mode->vdisplay;
> > +Â Â Âvactive = mode->vdisplay;
> > +
> > +Â Â Âhtime2 = (hfront_porch << 16) + hactive;
> > +Â Â Âvtime2 = (vfront_porch << 16) + vactive;
> > +
> > +Â Â Âval = d2l_read(tc->i2c, IDREG);
> > +
> > +Â Â Âdev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x
> **\n",
> > +Â Â Â Â Â Â Â (val >> 8) & 0xFF, val & 0xFF);
> > +
> > +Â Â Âd2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX |
> SYS_RST_BM |
> > +Â Â Â Â Â Â Â ÂSYS_RST_LCD | SYS_RST_I2CM | SYS_RST_I2CS);
> > +Â Â Âusleep_range(30000, 40000);
> > +
> > +Â Â Âd2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
> > +Â Â Âd2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
> > +Â Â Âd2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
> > +Â Â Âd2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
> > +Â Â Âd2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
> > +Â Â Âd2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
> > +
> > +Â Â Âval = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
> > +Â Â Âd2l_write(tc->i2c, PPI_LANEENABLE, val);
> > +Â Â Âd2l_write(tc->i2c, DSI_LANEENABLE, val);
> > +
> > +Â Â Âd2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
> > +Â Â Âd2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
> > +
> > +Â Â Âif (tc->bpc == 8)
> > +Â Â Â Â Â Â Âval = TC358775_VPCTRL_OPXLFMT(1);
> > +Â Â Âelse /* bpc = 6; */
> > +Â Â Â Â Â Â Âval = TC358775_VPCTRL_MSF(1);
> > +
> > +Â Â Âdsiclk = mode->crtc_clock * 3 * tc->bpc /
> tc->num_dsi_lanes / 1000;
> > +Â Â Âclkdiv = dsiclk / DIVIDE_BY_3 * tc->lvds_link;
> > +Â Â Âbyteclk = dsiclk / 4;
> > +Â Â Ât1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
> > +Â Â Ât2 = ((100000 / clkdiv)) * (hactive + hback_porch +
> hsync_len + hfront_porch) / 1000;
> > +Â Â Ât3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
> > +Â Â Â Â Â Â Âtc->num_dsi_lanes);
> > +
> > +Â Â Âvsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch -
> hsync_len - hactive;
> > +
> > +Â Â Âval |= TC358775_VPCTRL_VSDELAY(vsdelay);
> > +Â Â Âd2l_write(tc->i2c, VPCTRL, val);
> > +
> > +Â Â Âd2l_write(tc->i2c, HTIM1, htime1);
> > +Â Â Âd2l_write(tc->i2c, VTIM1, vtime1);
> > +Â Â Âd2l_write(tc->i2c, HTIM2, htime2);
> > +Â Â Âd2l_write(tc->i2c, VTIM2, vtime2);
> > +
> > +Â Â Âd2l_write(tc->i2c, VFUEN, VFUEN_EN);
> > +Â Â Âd2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
> > +Â Â Âd2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) |
> LV_PHY0_ND(6));
> > +
> > +Â Â Âdev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
> > +Â Â Â Â Â Â Âconnector->display_info.bus_formats[0],
> > +Â Â Â Â Â Â Âtc->bpc);
> > +Â Â Â/*
> > +Â Â Â * Default hardware register settings of tc358775 configured
> > +Â Â Â * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format
> > +Â Â Â */
> > +Â Â Âif (connector->display_info.bus_formats[0] ==
> > +Â Â Â Â Â Â ÂMEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
> > +Â Â Â Â Â Â Â/* VESA-24 */
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0,
> LVI_R1, LVI_R2, LVI_R3));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4,
> LVI_R7, LVI_R5, LVI_G0));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1,
> LVI_G2, LVI_G6, LVI_G7));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3,
> LVI_G4, LVI_G5, LVI_B0));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6,
> LVI_B7, LVI_B1, LVI_B2));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3,
> LVI_B4, LVI_B5, LVI_L0));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS,
> LVI_VS, LVI_DE, LVI_R6));
> > +Â Â Â} else { /*Â MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0,
> LVI_R1, LVI_R2, LVI_R3));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4,
> LVI_L0, LVI_R5, LVI_G0));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1,
> LVI_G2, LVI_L0, LVI_L0));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3,
> LVI_G4, LVI_G5, LVI_B0));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0,
> LVI_L0, LVI_B1, LVI_B2));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3,
> LVI_B4, LVI_B5, LVI_L0));
> > +Â Â Â Â Â Â Âd2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS,
> LVI_VS, LVI_DE, LVI_L0));
> > +Â Â Â}
> > +
> > +Â Â Âd2l_write(tc->i2c, VFUEN, VFUEN_EN);
> > +
> > +Â Â Âval = LVCFG_LVEN_BIT;
> > +Â Â Âif (tc->lvds_link == DUAL_LINK) {
> > +Â Â Â Â Â Â Âval |= TC358775_LVCFG_LVDLINK(1);
> > +Â Â Â Â Â Â Âval |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
> > +Â Â Â} else {
> > +Â Â Â Â Â Â Âval |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
> > +Â Â Â};
> > +Â Â Âd2l_write(tc->i2c, LVCFG, val);
> > +}
> > +
> > +static enum drm_mode_status
> > +tc_mode_valid(struct drm_bridge *bridge,
> > +Â Â Â Â Â Âconst struct drm_display_info *info,
> > +Â Â Â Â Â Âconst struct drm_display_mode *mode)
> > +{
> > +Â Â Âstruct tc_data *tc = bridge_to_tc(bridge);
> > +
> > +Â Â Â/*
> > +Â Â Â * Maximum pixel clock speed 135MHz for single-link
> > +Â Â Â * 270MHz for dual-link
> > +Â Â Â */
> > +Â Â Âif ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
> > +Â Â Â Â Â(mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
> > +Â Â Â Â Â Â Âreturn MODE_CLOCK_HIGH;
> > +
> > +Â Â Âswitch (info->bus_formats[0]) {
> > +Â Â Âcase MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
> > +Â Â Âcase MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> > +Â Â Â Â Â Â Â/* RGB888 */
> > +Â Â Â Â Â Â Âtc->bpc = 8;
> > +Â Â Â Â Â Â Âbreak;
> > +Â Â Âcase MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
> > +Â Â Â Â Â Â Â/* RGB666 */
> > +Â Â Â Â Â Â Âtc->bpc = 6;
> > +Â Â Â Â Â Â Âbreak;
> > +Â Â Âdefault:
> > +Â Â Â Â Â Â Âdev_warn(tc->dev,
> > +Â Â Â Â Â Â Â Â Â Â Â "unsupported LVDS bus format 0x%04x\n",
> > +Â Â Â Â Â Â Â Â Â Â Â info->bus_formats[0]);
> > +Â Â Â Â Â Â Âreturn MODE_NOMODE;
> > +Â Â Â}
> > +
> > +Â Â Âreturn MODE_OK;
> > +}
> > +
> > +static int tc358775_parse_dt(struct device_node *np, struct
> tc_data *tc)
> > +{
> > +Â Â Âstruct device_node *endpoint;
> > +Â Â Âstruct device_node *parent;
> > +Â Â Âstruct device_node *remote;
> > +Â Â Âstruct property *prop;
> > +Â Â Âint len = 0;
> > +
> > +Â Â Â/*
> > +Â Â Â * To get the data-lanes of dsi, we need to access the
> dsi0_out of port1
> > +Â Â Â *Â of dsi0 endpoint from bridge port0 of d2l_in
> > +Â Â Â */
> > +Â Â Âendpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
> > + TC358775_DSI_IN, -1);
> > +Â Â Âif (endpoint) {
> > +Â Â Â Â Â Â Â/* dsi0_out node */
> > +Â Â Â Â Â Â Âparent = of_graph_get_remote_port_parent(endpoint);
> > +Â Â Â Â Â Â Âof_node_put(endpoint);
> > +Â Â Â Â Â Â Âif (parent) {
> > +Â Â Â Â Â Â Â Â Â Â Â/* dsi0 port 1 */
> > +Â Â Â Â Â Â Â Â Â Â Âendpoint =
> of_graph_get_endpoint_by_regs(parent, 1, -1);
> > +Â Â Â Â Â Â Â Â Â Â Âof_node_put(parent);
> > +Â Â Â Â Â Â Â Â Â Â Âif (endpoint) {
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âprop = of_find_property(endpoint,
> "data-lanes",
> > + Â&len);
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âof_node_put(endpoint);
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âif (!prop) {
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âdev_err(tc->dev,
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â"failed to find
> data lane\n");
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âreturn -EPROBE_DEFER;
>
>
> probe defer here looks crazy :) do you expect "data-lanes"
> property will
> appear later? Theoretically it is possible.
>
> Other thing that bothers me is "data-lanes" property - lots of tree
> walking code, error prone, lurking into other's device nodes - all
> that
> to get one number.
>
> Either there should be helpers for it (maybe there are some already),
> either it should be done differently. Laurent, Neil, Jonas, Jernej
> any
> thoughts?
>
>
> Regards
>
> Andrzej
>
>
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â}
> > +Â Â Â Â Â Â Â Â Â Â Â}
> > +Â Â Â Â Â Â Â}
> > +Â Â Â}
> > +
> > +Â Â Âtc->num_dsi_lanes = len / sizeof(u32);
> > +
> > +Â Â Âif (tc->num_dsi_lanes < 1 || tc->num_dsi_lanes > 4)
> > +Â Â Â Â Â Â Âreturn -EINVAL;
> > +
> > +Â Â Âtc->host_node = of_graph_get_remote_node(np, 0, 0);
> > +Â Â Âif (!tc->host_node)
> > +Â Â Â Â Â Â Âreturn -ENODEV;
> > +
> > +Â Â Âof_node_put(tc->host_node);
> > +
> > +Â Â Âtc->lvds_link = SINGLE_LINK;
> > +Â Â Âendpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
> > + TC358775_LVDS_OUT1, -1);
> > +Â Â Âif (endpoint) {
> > +Â Â Â Â Â Â Âremote = of_graph_get_remote_port_parent(endpoint);
> > +Â Â Â Â Â Â Âof_node_put(endpoint);
> > +
> > +Â Â Â Â Â Â Âif (remote) {
> > +Â Â Â Â Â Â Â Â Â Â Âif (of_device_is_available(remote))
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âtc->lvds_link = DUAL_LINK;
> > +Â Â Â Â Â Â Â Â Â Â Âof_node_put(remote);
> > +Â Â Â Â Â Â Â}
> > +Â Â Â}
> > +
> > +Â Â Âdev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
> > +Â Â Âdev_dbg(tc->dev, "operating in %d-link mode\n",
> tc->lvds_link);
> > +
> > +Â Â Âreturn 0;
> > +}
> > +
> > +static int tc_bridge_attach(struct drm_bridge *bridge,
> > +Â Â Â Â Â Â Â Â Â Â Â Â Âenum drm_bridge_attach_flags flags)
> > +{
> > +Â Â Âstruct tc_data *tc = bridge_to_tc(bridge);
> > +Â Â Âstruct device *dev = &tc->i2c->dev;
> > +Â Â Âstruct mipi_dsi_host *host;
> > +Â Â Âstruct mipi_dsi_device *dsi;
> > +Â Â Âint ret;
> > +
> > +Â Â Âconst struct mipi_dsi_device_info info = { .type = "tc358775",
> > + Â.channel = 0,
> > + Â.node = NULL,
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â};
> > +
> > +Â Â Âhost = of_find_mipi_dsi_host_by_node(tc->host_node);
> > +Â Â Âif (!host) {
> > +Â Â Â Â Â Â Âdev_err(dev, "failed to find dsi host\n");
> > +Â Â Â Â Â Â Âreturn -EPROBE_DEFER;
> > +Â Â Â}
> > +
> > +Â Â Âdsi = mipi_dsi_device_register_full(host, &info);
> > +Â Â Âif (IS_ERR(dsi)) {
> > +Â Â Â Â Â Â Âdev_err(dev, "failed to create dsi device\n");
> > +Â Â Â Â Â Â Âret = PTR_ERR(dsi);
> > +Â Â Â Â Â Â Âgoto err_dsi_device;
> > +Â Â Â}
> > +
> > +Â Â Âtc->dsi = dsi;
> > +
> > +Â Â Âdsi->lanes = tc->num_dsi_lanes;
> > +Â Â Âdsi->format = MIPI_DSI_FMT_RGB888;
> > +Â Â Âdsi->mode_flags = MIPI_DSI_MODE_VIDEO;
> > +
> > +Â Â Âret = mipi_dsi_attach(dsi);
> > +Â Â Âif (ret < 0) {
> > +Â Â Â Â Â Â Âdev_err(dev, "failed to attach dsi to host\n");
> > +Â Â Â Â Â Â Âgoto err_dsi_attach;
> > +Â Â Â}
> > +
> > +Â Â Â/* Attach the panel-bridge to the dsi bridge */
> > +Â Â Âreturn drm_bridge_attach(bridge->encoder, tc->panel_bridge,
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &tc->bridge, flags);
> > +err_dsi_attach:
> > +Â Â Âmipi_dsi_device_unregister(dsi);
> > +err_dsi_device:
> > +Â Â Âreturn ret;
> > +}
> > +
> > +static const struct drm_bridge_funcs tc_bridge_funcs = {
> > +Â Â Â.attach = tc_bridge_attach,
> > +Â Â Â.pre_enable = tc_bridge_pre_enable,
> > +Â Â Â.enable = tc_bridge_enable,
> > +Â Â Â.mode_valid = tc_mode_valid,
> > +Â Â Â.post_disable = tc_bridge_post_disable,
> > +};
> > +
> > +static int tc_probe(struct i2c_client *client, const struct
> i2c_device_id *id)
> > +{
> > +Â Â Âstruct device *dev = &client->dev;
> > +Â Â Âstruct drm_panel *panel;
> > +Â Â Âstruct tc_data *tc;
> > +Â Â Âint ret;
> > +
> > +Â Â Âtc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
> > +Â Â Âif (!tc)
> > +Â Â Â Â Â Â Âreturn -ENOMEM;
> > +
> > +Â Â Âtc->dev = dev;
> > +Â Â Âtc->i2c = client;
> > +
> > +Â Â Âret = drm_of_find_panel_or_bridge(dev->of_node,
> TC358775_LVDS_OUT0,
> > +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â0, &panel, NULL);
> > +Â Â Âif (ret < 0)
> > +Â Â Â Â Â Â Âreturn ret;
> > +Â Â Âif (!panel)
> > +Â Â Â Â Â Â Âreturn -ENODEV;
> > +
> > +Â Â Âtc->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
> > +Â Â Âif (IS_ERR(tc->panel_bridge))
> > +Â Â Â Â Â Â Âreturn PTR_ERR(tc->panel_bridge);
> > +
> > +Â Â Âret = tc358775_parse_dt(dev->of_node, tc);
> > +Â Â Âif (ret)
> > +Â Â Â Â Â Â Âreturn ret;
> > +
> > +Â Â Âtc->vddio = devm_regulator_get(dev, "vddio-supply");
> > +Â Â Âif (IS_ERR(tc->vddio)) {
> > +Â Â Â Â Â Â Âret = PTR_ERR(tc->vddio);
> > +Â Â Â Â Â Â Âdev_err(dev, "vddio-supply not found\n");
> > +Â Â Â Â Â Â Âreturn ret;
> > +Â Â Â}
> > +
> > +Â Â Âtc->vdd = devm_regulator_get(dev, "vdd-supply");
> > +Â Â Âif (IS_ERR(tc->vdd)) {
> > +Â Â Â Â Â Â Âret = PTR_ERR(tc->vddio);
> > +Â Â Â Â Â Â Âdev_err(dev, "vdd-supply not found\n");
> > +Â Â Â Â Â Â Âreturn ret;
> > +Â Â Â}
> > +
> > +Â Â Âtc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH);
> > +Â Â Âif (IS_ERR(tc->stby_gpio)) {
> > +Â Â Â Â Â Â Âret = PTR_ERR(tc->stby_gpio);
> > +Â Â Â Â Â Â Âdev_err(dev, "cannot get stby-gpio %d\n", ret);
> > +Â Â Â Â Â Â Âreturn ret;
> > +Â Â Â}
> > +
> > +Â Â Âtc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
> > +Â Â Âif (IS_ERR(tc->reset_gpio)) {
> > +Â Â Â Â Â Â Âret = PTR_ERR(tc->reset_gpio);
> > +Â Â Â Â Â Â Âdev_err(dev, "cannot get reset-gpios %d\n", ret);
> > +Â Â Â Â Â Â Âreturn ret;
> > +Â Â Â}
> > +
> > +Â Â Âtc->bridge.funcs = &tc_bridge_funcs;
> > +Â Â Âtc->bridge.of_node = dev->of_node;
> > +Â Â Âdrm_bridge_add(&tc->bridge);
> > +
> > +Â Â Âi2c_set_clientdata(client, tc);
> > +
> > +Â Â Âreturn 0;
> > +}
> > +
> > +static int tc_remove(struct i2c_client *client)
> > +{
> > +Â Â Âstruct tc_data *tc = i2c_get_clientdata(client);
> > +
> > +Â Â Âdrm_bridge_remove(&tc->bridge);
> > +
> > +Â Â Âreturn 0;
> > +}
> > +
> > +static const struct i2c_device_id tc358775_i2c_ids[] = {
> > +Â Â Â{ "tc358775", 0 },
> > +Â Â Â{ }
> > +};
> > +MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
> > +
> > +static const struct of_device_id tc358775_of_ids[] = {
> > +Â Â Â{ .compatible = "toshiba,tc358775", },
> > +Â Â Â{ }
> > +};
> > +MODULE_DEVICE_TABLE(of, tc358775_of_ids);
> > +
> > +static struct i2c_driver tc358775_driver = {
> > +Â Â Â.driver = {
> > +Â Â Â Â Â Â Â.name = "tc358775",
> > +Â Â Â Â Â Â Â.of_match_table = tc358775_of_ids,
> > +Â Â Â},
> > +Â Â Â.id_table = tc358775_i2c_ids,
> > +Â Â Â.probe = tc_probe,
> > +Â Â Â.remove = tc_remove,
> > +};
> > +module_i2c_driver(tc358775_driver);
> > +
> > +MODULE_AUTHOR("Vinay Simha BN <simhavcs@xxxxxxxxx
> <mailto:simhavcs@xxxxxxxxx>>");
> > +MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
> > +MODULE_LICENSE("GPL v2");
>
>
>
> --
> regards,
> vinaysimha
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

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