drivers/pci/controller/dwc/pcie-spear13xx.c:76:54: sparse: sparse: incorrect type in initializer (different address spaces)

From: kernel test robot
Date: Sun Jul 12 2020 - 15:24:50 EST

tree: .config.gz
Description: application/gzip Pavel Machek: "Re: [PATCH RFC] leds: Add support for per-LED device triggers" Jiri Olsa: "Re: [RFC v2 0/5] tools/perf/pmu-events/jevents.c" date ] [ thread ] [ subject ] [ author ] /linux/kernel/git/torvalds/linux.git">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
use identifiers to define address spaces
r> r> ARCH=x86_64
r> sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct pcie_app_reg *app_reg @@ got void [noderef] __iomem *app_base @@
expected struct pcie_app_reg *app_reg
got void [noderef] __iomem *app_base
sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got unsigned int * @@
expected void volatile [noderef] __iomem *addr
got unsigned int *
sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct pcie_app_reg *app_reg @@ got void [noderef] __iomem *app_base @@
expected struct pcie_app_reg *app_reg
got void [noderef] __iomem *app_base
sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got unsigned int * @@
expected void const volatile [noderef] __iomem *addr
got unsigned int *
sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got unsigned int * @@
expected void volatile [noderef] __iomem *addr
got unsigned int *
sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct pcie_app_reg *app_reg @@ got void [noderef] __iomem *app_base @@
expected struct pcie_app_reg *app_reg
got void [noderef] __iomem *app_base
sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got unsigned int * @@
expected void const volatile [noderef] __iomem *addr
got unsigned int *
sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got unsigned int * @@
expected void volatile [noderef] __iomem *addr
got unsigned int *
sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct pcie_app_reg *app_reg @@ got void [noderef] __iomem *app_base @@
expected struct pcie_app_reg *app_reg
got void [noderef] __iomem *app_base
sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got unsigned int * @@
expected void const volatile [noderef] __iomem *addr
got unsigned int *
2014-02-11 71
2016-10-06 72 static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
2014-02-11 73 {
Vijay Abraham I 2017-02-15 74 struct dw_pcie *pci = spear13xx_pcie->pci;
Vijay Abraham I 2017-02-15 75 struct pcie_port *pp = &pci->pp;
2014-02-11 @76 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
2016-10-06 77 u32 val;
2014-02-11 78 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
2014-02-11 79
Vijay Abraham I 2017-02-15 80 if (dw_pcie_link_up(pci)) {
Vijay Abraham I 2017-02-15 81 dev_err(pci->dev, "link already up\n");
2014-02-11 82 return 0;
2014-02-11 83 }
2014-02-11 84
2014-02-11 85 dw_pcie_setup_rc(pp);
2014-02-11 86
2014-02-11 87 /*
2014-02-11 88 * this controller support only 128 bytes read size, however its
2014-02-11 89 * default value in capability register is 512 bytes. So force
2014-02-11 90 * it to 128 here.
2014-02-11 91 */
Vijay Abraham I 2017-02-15 92 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
2014-02-11 93 val &= ~PCI_EXP_DEVCTL_READRQ;
Vijay Abraham I 2017-02-15 94 dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
2014-02-11 95
Vijay Abraham I 2017-02-15 96 dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
Vijay Abraham I 2017-02-15 97 dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
2014-02-11 98
2014-02-11 99 /*
2014-02-11 100 * if is_gen1 is set then handle it, so that some buggy card
2014-02-11 101 * also works
2014-02-11 102 */
2014-02-11 103 if (spear13xx_pcie->is_gen1) {
Vijay Abraham I 2017-02-15 104 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
2015-10-08 105 4, &val);
2014-02-11 106 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
2014-02-11 107 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
2014-02-11 108 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
Vijay Abraham I 2017-02-15 109 dw_pcie_write(pci->dbi_base + exp_cap_off +
2015-10-08 110 PCI_EXP_LNKCAP, 4, val);
2014-02-11 111 }
2014-02-11 112
Vijay Abraham I 2017-02-15 113 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
2015-10-08 114 2, &val);
2014-02-11 115 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
2014-02-11 116 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
2014-02-11 117 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
Vijay Abraham I 2017-02-15 118 dw_pcie_write(pci->dbi_base + exp_cap_off +
2015-10-08 119 PCI_EXP_LNKCTL2, 2, val);
2014-02-11 120 }
2014-02-11 121 }
2014-02-11 122
2014-02-11 123 /* enable ltssm */
2014-02-11 124 writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
2014-02-11 125 | (1 << APP_LTSSM_ENABLE_ID)
2014-02-11 126 | ((u32)1 << REG_TRANSLATION_ENABLE),
2014-02-11 @127 &app_reg->app_ctrl_0);
2014-02-11 128
Vijay Abraham I 2017-02-15 129 return dw_pcie_wait_for_link(pci);
2014-02-11 130 }
2014-02-11 131
2014-02-11 132 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
2014-02-11 133 {
2016-10-06 134 struct spear13xx_pcie *spear13xx_pcie = arg;
2014-02-11 135 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
Vijay Abraham I 2017-02-15 136 struct dw_pcie *pci = spear13xx_pcie->pci;
Vijay Abraham I 2017-02-15 137 struct pcie_port *pp = &pci->pp;
2014-02-11 138 unsigned int status;
2014-02-11 139
2014-02-11 @140 status = readl(&app_reg->int_sts);
2014-02-11 141
2014-02-11 142 if (status & MSI_CTRL_INT) {
2015-08-20 143 BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
2014-02-11 144 dw_handle_msi_irq(pp);
2014-02-11 145 }
2014-02-11 146
2014-02-11 147 writel(status, &app_reg->int_clr);
2014-02-11 148
2014-02-11 149 return IRQ_HANDLED;
2014-02-11 150 }
2014-02-11 151
Add PCIe driver for ST Microelectronics SPEAr13xx
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