Re: [PATCH v9 0/2] Adding support for Versal CPM as Root Port driver

[Lorenzo Pieralisi]

On Tue, Jun 16, 2020 at 06:26:52PM +0530, Bharat Kumar Gogada wrote:
> - Adding support for Versal CPM as Root port.
> - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
>   block for CPM along with the integrated bridge can function
>   as PCIe Root Port.
> - Versal CPM uses GICv3 ITS feature for assigning MSI/MSI-X
>   vectors and handling MSI/MSI-X interrupts.
> - Bridge error and legacy interrupts in Versal CPM are handled using
>   Versal CPM specific interrupt line.
> 
> Changes for v9:
> - Removed interrupt enablement outside irqchip flow as suggested
>   by Marc.
> - Removed using WARN_ON in if statement.
> 
> Bharat Kumar Gogada (2):
>   PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port
>   PCI: xilinx-cpm: Add Versal CPM Root Port driver
> 
>  .../devicetree/bindings/pci/xilinx-versal-cpm.yaml |  99 ++++
>  drivers/pci/controller/Kconfig                     |   8 +
>  drivers/pci/controller/Makefile                    |   1 +
>  drivers/pci/controller/pcie-xilinx-cpm.c           | 615 +++++++++++++++++++++
>  4 files changed, 723 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
>  create mode 100644 drivers/pci/controller/pcie-xilinx-cpm.c

Applied to pci/xilinx (I removed a function kerneldoc comment
(xilinx_cpm_pcie_clear_err_interrupts()) since it was not matching
the function name and honestly it is not really needed) for v5.9.

Thanks,
Lorenzo